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HBM2E PHY&Controller

Overview

Innosilicon HBM2E PHY IP is a silicon proven product with max speed up to 3600Mbps per DQ data, HBM2E memory has 1024bit DQ, total bandwidth can be 3.6Tbps. Innosilicon HBM2E PHY IP can support both 4 Hi and 8 Hi memory type.
This document describes a general layout scheme and DDR controller connecting to Innosilicon combo PHY using a DFI digital interface. All interface timing is in 1X SDR clock domain. This Interface is flexible and can be converted to any customer desired format and timing sequence. The controller to PHY interface is running at single data rate (SDR) therefore read/write bus is double width. DDR muxing is done in the PHY block together with all related per-byte lane timing adjustment.

Key Features

  • Compliant with JESD235C HBM2E, up to 3200Mbps
  • Compliant with DFI 3.1 Specifications (dfi_clk_1x : wdqs = 1:2)
  • Support up to 8 Channel with 128 DQ width + Optional ECC pin support/channel
  • Support command and DQ parity
  • Support per-Aword De-skew tuning for Command
  • Support per-Dword De-skew tuning for Data
  • Support CMD lane repair
  • Support DQ lane repair
  • Support Automatic /Soft Command Bus Training
  • Support Command/Data IO Driver Strength adjustment
  • Support Automatic /Soft RX DQS Training/Bypass RX DQS Control
  • Support Automatic /Soft WDQS2CK Training/Bypass WDQS2CK Control
  • Support Automatic /Soft Read Training
  • Support Automatic /Soft Write Training
  • Support Bypass Write Training/Read Training
  • Support ZQ calibration
  • Support Built-In Self-Test
  • Support Boundary Scan of pad
  • Support scan chain
  • APB 3.0 interfaces to configure registers
  • Support IEEE1500 port for direct access to the memory stack and PHY by using APB
  • Support HBM DRAM initial by PHY

Benefits

  • Substantially increases bandwidth available to computing devices
  • Fully pre-assemble design, drop-in hard macro to ease integration and speed time to market
  • Offers leading performance, power, and area per terabit
  • Extensive EDA tool support for various design automation flows
  • DFT functions to reduce test time and ensure high test coverage
  • Proven capabilities in PHY and silicon interposer design and integration
  • Optional PI/SI and thermal co-design service
  • Full support from IP delivery to production

Applications

  • High performance computing
  • Artificial intelligence
  • GPU

Deliverables

  • Databook and physical implementation guides
  • Netlist (Spice format for LVS)
  • Library Exchange Format (LEF)
  • Verilog Models
  • GDSII to Foundry IP Merge
  • Module integration guidelines
  • Silicon validation report (when available)
  • Evaluation board (when available)

Technical Specifications

Foundry, Node
TSMC 7nm, SMIC14nm
SMIC
In Production: 14nm
Silicon Proven: 14nm
TSMC
In Production: 7nm
Silicon Proven: 7nm
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