Four-Wire Slave Interface for M8051W and M8051EW Microcontrollers

Overview

Key Features

• Implementation of a four-wire synchronous full-duplex slave interface, compatible with the Motorola SPI bus
• Supports various message protocols using byte granularity data
• Programmable clock phase and clock and select polarity
• Supports any four-wire clock rate, independent of microcontroller clock rate
• Integral transmit and receive data FIFOs minimise the processor overhead required to service the link
• Supports both interrupt-driven and polled transfers
• Optional clock prescaler minimises power consumption while active
• Rests in power saving mode when the interface is not enabled
• Slave select wake up feature can be used to cold start a M8051W and M8051EW microcontroller, in addition to interrupt driven wake ups
• Binds tightly to M8051W and M8051EW external interrupt and SFR buses with no additional glue logic required

Deliverables

• VHDL 93 and Verilog 2001 RTL source code
• VHDL and Verilog functional demonstration testbench
• Demonstration assembler code
• Simulation scripts for Modelsim and Cadence
• Synopsys synthesis compile scripts and SDC timing constraint files
• Example Mentor DFT and ATPG scripts
• Example netlist implementation with SDF files
• Detailed product specification and a user guide containing implementation note

Technical Specifications