A 65nm Wirebond IO library with 2.5V GPIO, LVDS TX & RX and 2.5V analog / RF

Overview

Key attributes of the GlobalFoundries 65nm IO library are dual selectable drive strengths and independent input & output enable / disable. The GPIO cell can be configured as input, output or open-drain with a Schmitt trigger input and selectable internal 60K ohm pull-up or pull-down resistor. ESD protection for IO and core supplies is constructed in an aggressive footprint. 2.5V LVDS RX & TX cells capable of data rates up to 1.5Gbps (with no external reference) and a 2.5V low-capacitance analog/RF cell complement the GPIO offering. The library is enriched with filler, corner and domain-break cells to allow for flexible pad ring construction.

Built into our IO libraries, and also offered as a separate service, is our strong ESD expertise. Certus was founded by ESD engineers and our results speak for themselves. Not only do we consistently exceed the standard ESD targets of 2KV HBM and 500V CDM, but we also provide on-chip solutions for standards such as IEC-61000-4-2, system-level ESD and Cable Discharge Events (CDE).

Certus supports additional IO libraries in GlobalFoundries technologies, as well as at TSMC and Samsung. Certus is particularly suited at providing custom variants in a cost-efficient framework. Please contact us for supplementary physical or electrical features that can suit your needs.

Key Features

  • GPIO:
    • 2.5V nominal IO operation
    • Selectable 12mA | 24mA drive strength options
    • Up to 200MHz operation (@24mA, 10pF)
    • Output enable (HiZ when disabled)
    • Input enable (input low when disabled)
    • Schmitt trigger receiver
    • 60K? selectable pull-up or pull-down resistor
    • ESD: 2KV HBM, 500V CDM2
    • Silicon proven
  • LVDS TX & RX
    • 2.5V nominal operation
    • Data rates of 1.5Gbps
    • Output / Input enable
    • Built-in 100? RX termination resistor
    • Fault-safe mode for shorted or open RX pins
    • Internally generated common mode reference (no external pin required)
    • Power-on sequence independence
    • ESD protection of 2KV HBM, 500V CDM
  • ANALOG / RF
    • 2.5V tolerant
    • Low capacitance
    • 2KV HBM, 500V CDM
  • Physical Attributes
    • 8-metal stack - B1_EA
    • 45um x 200um cell size
    • 45um dual row wirebond pitch

Benefits

  • Selectable drive strengths
  • Independent input & output enable
  • Up to 200MHz operation
  • Customizable
  • Pull-up / pull-down resistor options
  • ANSI TIA/EIA-644-A compliant 2.5V LVDS RX & TX
  • Low-capacitance analog / RF cell
  • 45um dual row wirebond pitch
  • Silicon proven

Block Diagram

A 65nm Wirebond IO library with 2.5V GPIO, LVDS TX & RX and 2.5V analog / RF Block Diagram

Applications

  • LVCMOS GPIO, LVDS, RF/Analog

Deliverables

  • GDS
  • CDL netlist
  • Verilog stub
  • Verilog behavioral model
  • LEF
  • Liberty Timing Files
  • IBIS (option)
  • Electrical datasheet
  • User guide and application notes
  • Consulting and Support

Technical Specifications

Foundry, Node
GlobalFoundries 65nm LPe
Maturity
Silicon-Proven
Availability
Immediate
GLOBALFOUNDRIES
In Production: 65nm LPe
Pre-Silicon: 65nm LPe
Silicon Proven: 65nm LPe
×
Semiconductor IP