Standard Cell Library IP
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Standard Cell Library
- Basic Cells: A full suite of fundamental logic gates and flip-flops.
- Optimal Cells: High-performance variants of basic cells, optimized for power, area, and speed, including high-speed flip-flops, advanced multiplexers, clock gated cells, clock buffers, arithmetic cells and custom-designed cells for critical paths.
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Standard Cell Library, Low Voltaage TSMC N3P
- Nominal voltage of 0.75 V +/-10 %
- Low voltage of 0.45 V +/-10 %
- Track height: 7.5T
- Operating temperature: -40°C to 125°C
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Digital Standard Cell Library
- The agileDSCL is a compact Digital Standard Cell Library customizable for specific foundries and processes, and optimized for low-power, ultra-low-leakage, high-density or high-speed applications.
- It provides a selection of standard cells with functionalities essential to implement digital designs, with an additional power management library to support the implementation of low-power designs.
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SMIC 0.13um 6 track High Density Standard Cell Library - HVT,1.2v operating voltage
- SMIC 0.13um Logic 1P8M 1.2V/3.3V process
- Wide Variety of Cell Functions and Drive Strengths
- Process-Specific Optimization for High-Density, High-Speed, and Low-Power
- Engineered for Synthesizability and Routability
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6 track High Density standard cell library at TSMC 180nm
- High Density optimization