Frac-N PLL IP for UMC
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Frac-N PLL IP
for UMC
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3
Frac-N PLL IP
for UMC
from 2 vendors
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3)
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Integrated Droop Response System
- Observable
- Tightly Coupled
- Process Portable
-
Aeonic Generate Clock Generation Module [PLL], 8x smaller than fractional analog solutions
- Process portable
- Proven (65nm to 3nm)
- Full SCAN testable
- Core voltage supply
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10MHz to 50MHz fractional-N PLL synthesizer
- UMC 22nm ULP technology
- 1.8V IO power supply
- Double 0.8/1.0V Core power supply
- Embedded low noise bias