Hash and HMAC Accelerator IP for TSMC

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Compare 5 Hash and HMAC Accelerator IP for TSMC from 2 vendors (1 - 5)

TSMC CL015G 150nm Clock Generator PLL - 130MHz-650MHz
- Designed as a very flexible clock multiplier capable of multiplying an input clock from 1 to 4096 with very small period jitter while operating at the highest possible bandwidth.
- Delivers optimal jitter performance over all multiplication settings.
- Available with multi-phase outputs and, in some processes, with an I/O voltage regulator.
- Ideal for system clock generation, SerDes and video clock applications.
SM3 Crypto Accelerator
- Register interface.
- Widebus interface with native algorithm bus widths.
- Message padding functionality.
- Hash context switching
Poly1305 Crypto Accelerator
- Pipelined high speed Wide bus interface
- R Key and S Key inputs – 128-bit wide
- Digest input – 131-bit wide
- DMA and AEAD support
HASH Accelerator with SHA-3, SHA-2, SHA-1
- Wide bus interface (1024 bit data, 512 bit digest) or 32 bit register interface
- MD5, SHA-1, SHA-2, SHA-3
- SHA-2/3 in 224/256/384/512 modes
- Message puffing for all algorithms
HMAC Accelerator with SHA-3, SHA-2, SHA-1
- Wide bus interface
- Supporting HMAC and Basic Hash operations for all algorithms: MD5, SHA-1, SHA-2 (224, 256, 384, 512), SHA-3 (224, 256, 384, 512)
- MAC Key XOR and Message padding
- Message data scheduling hardware