HASH Accelerator with SHA-3, SHA-2, SHA-1

Overview

Key Features

• Wide bus interface (1024 bit data, 512 bit digest) or 32 bit register interface
• MD5, SHA-1, SHA-2, SHA-3
• SHA-2/3 in 224/256/384/512 modes
• Message puffing for all algorithms
• Message data scheduling hardware
• Hash context switching and state loading
• Standard, high frequency and high performance versions available
• Fully synchronous design

Benefits

• High-speed MD5/SHA-1/SHA-2/SHA-3 solution
• Silicon-proven implementation
• Fast and easy to integrate into SoCs
• Flexible layered design
• Complete range of configurations
• World-class technical support

Applications

• Hash
• Key exchange
• Authentication
• SSL
• TLS
• DLTS
• IPsec
• Communication protocols

Deliverables

• Documentation
• Hardware Reference and Programmer Manual
• Integration Manual
• Verification Specification
• Synthesizable Verilog RTL source code
• Self-checking RTL test bench, including test vectors and expected result vectors
• Simulation scripts
• Synthesis scripts
• Many different configurations available:
• Single algorithms:
• MD5 / SHA-1 / SHA-2 / SHA-3
• Support for all algorithms and standards.
• Various combinations of algorithms, including but not limited to:
• SHA-1, SHA-2, SHA-3 (all variants)
• SHA-1, SHA-2-224/256, SHA-3 (all variants)
• MD5, SHA-1, SHA-2 (all variants)
• SHA-1, SHA-2-224/256
• Various speed grades available for each of the algorithms.
• PERFORMANCE
• MD5 performance ranges from 3.96 to 15.5 bits/clk achieving over 7Gbit/sec at maximum frequency.
• SHA-1 performance ranges from 6.32 to 12.5 bits/clk achieving over 8Gbit/sec at maximum frequency.
• SHA-2-224/256 performance ranges from 7.88 to 15.5 bits/clk achieving over 7Gbit/sec at maximum frequency.
• SHA-2-384/512 performance is 12.6 bits/clk achieving over 10Gbit/sec at maximum frequency.
• SHA-3-224 performance is 144.0 bits/clk achieving over 84Gbit/sec at maximum frequency.
• SHA-3-256 performance is 136.0 bits/clk achieving over 80Gbit/sec at maximum frequency.
• SHA-3-384 performance is 104.0 bits/clk achieving over 61Gbit/sec at maximum frequency.
• SHA-3-512 performance is 72.0 bits/clk achieving over 42Gbit/sec at maximum frequency.
• GATE COUNTS
• The gate counts for a single algorithm engine ranges from 14k gates for MD5 or SHA- cores to approximately 41k gates for a full SHA-2 or 49k gates for a full SHA-3 core.
• An engine supporting all algorithms is available within 81k gates.
• For more information about this product or the all the different configurations, please contact Rambus: https://www.rambus.com/contact

Technical Specifications