Multi-Protocol PHY IP for TSMC
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Multi-Protocol PHY IP
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Multi-Protocol PHY IP
for TSMC
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10Gbps Multi-Link and Multi-Protocol PCIe 3.1 PHY IP for TSMC
- Supports USB 3.1, PCIe 3.0/2.0/1.0, DP-TX v1.4/ eDP-TX v1.4b, SATA 3, 10G-KR and SGMII
- Supports PCIe L1 sub-states
- Supports SRIS and internal SSC generation
- Supports internal and external clock sources with clock active detection
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25G PHY, TSMC 7FF x4 North/South (vertical) poly orientation
- Supports 1.25 to 25.8 Gbps data-rate
- Supports PCI Express 4.0 with lane margining, 1G to 100G Ethernet, CCIX, and SATA protocols
- Supports x1 to x16 macro configurations with aggregation and bifurcation
- Spread Spectrum Clock (SSC), ` PCIe Separate Refclk Independent SSC (SRIS) and power management features
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25G PHY, TSMC 7FF x2 North/South (vertical) poly orientation
- Supports 1.25 to 25.8 Gbps data-rate
- Supports PCI Express 4.0 with lane margining, 1G to 100G Ethernet, CCIX, and SATA protocols
- Supports x1 to x16 macro configurations with aggregation and bifurcation
- Spread Spectrum Clock (SSC), ` PCIe Separate Refclk Independent SSC (SRIS) and power management features
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25G PHY, TSMC 7FF x1 North/South (vertical) poly orientation
- Supports 1.25 to 25.8 Gbps data-rate
- Supports PCI Express 4.0 with lane margining, 1G to 100G Ethernet, CCIX, and SATA protocols
- Supports x1 to x16 macro configurations with aggregation and bifurcation
- Spread Spectrum Clock (SSC), ` PCIe Separate Refclk Independent SSC (SRIS) and power management features
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25G MR Ethernet PHY, TSMC 7FF x4 North/South (vertical) poly orientation
- Supports 1.25 to 25.8 Gbps data-rate
- Supports PCI Express 4.0 with lane margining, 1G to 100G Ethernet, CCIX, and SATA protocols
- Supports x1 to x16 macro configurations with aggregation and bifurcation
- Spread Spectrum Clock (SSC), ` PCIe Separate Refclk Independent SSC (SRIS) and power management features
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25G MR Ethernet PHY, TSMC 7FF x2 North/South (vertical) poly orientation
- Supports 1.25 to 25.8 Gbps data-rate
- Supports PCI Express 4.0 with lane margining, 1G to 100G Ethernet, CCIX, and SATA protocols
- Supports x1 to x16 macro configurations with aggregation and bifurcation
- Spread Spectrum Clock (SSC), ` PCIe Separate Refclk Independent SSC (SRIS) and power management features
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16G LP PHY, TSMC N7 x4, North/South (vertical) poly orientation for Automotive, ASIL B Random, AEC-Q100 Grade 2
- Supports 1.25 to 16 Gbps data rates
- Supports PCI Express,IEEE 802.3, SGMII and QSGMII,SATA, CEI-6G and CEI-11G, Serial Rapid IO (SRIO), CPRI, OBSAI, JESD204B
- Supports x1 to x16 macro configurations
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16G LP PHY, TSMC N7 x4, North/South (vertical) poly orientation
- Supports 1.25 to 16 Gbps data rates
- Supports PCI Express,IEEE 802.3, SGMII and QSGMII,SATA, CEI-6G and CEI-11G, Serial Rapid IO (SRIO), CPRI, OBSAI, JESD204B
- Supports x1 to x16 macro configurations
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16G LP PHY, TSMC N7 x2, North/South (vertical) poly orientation for Automotive, ASIL B Random, AEC-Q100 Grade 2
- Supports 1.25 to 16 Gbps data rates
- Supports PCI Express,IEEE 802.3, SGMII and QSGMII,SATA, CEI-6G and CEI-11G, Serial Rapid IO (SRIO), CPRI, OBSAI, JESD204B
- Supports x1 to x16 macro configurations
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16G LP PHY, TSMC N7 x2, North/South (vertical) poly orientation
- Supports 1.25 to 16 Gbps data rates
- Supports PCI Express,IEEE 802.3, SGMII and QSGMII,SATA, CEI-6G and CEI-11G, Serial Rapid IO (SRIO), CPRI, OBSAI, JESD204B
- Supports x1 to x16 macro configurations
