MIPI D-PHY IP for TSMC
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MIPI D-PHY IP
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MIPI D-PHY IP
for TSMC
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- 7nm
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MIPI C-PHY/D-PHY Combo RX IP 4.5Gsps/4.5Gbps in TSMC N7
- Dual mode PHY Supports MIPI Alliance Specification D-PHYv2.5 & C-PHYv2.0
- Consists of 1 Clock lane and 4 Data lanes in D-PHYmode
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MIPI D-PHY IP 4.5Gbps in TSMC N7
- Supports MIPI Alliance Specification for D-PHY Version 2.5
- Consists of 1 Clock lane and 4 Data lanes
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MIPI D-PHY
- Multiple Configurations Possible. TX-only (with integrated PLL), RX-only, and combined TX and RX configurations
- Complete Function for HS TX/RX, LP TX/RX, and LPCD with automatic termination control for high-speed and low-power modes
- Integrated BIST Capable of producing and checking PRBS, CRPAT, and CJTPAT
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MIPI D-PHY Tx 4 Lanes - TSMC7FF18, North/South Poly Orientation
- Compliant with the MIPI D-PHY specification, v1.2
- Fully integrated hard macro
- Up to 2.5 Gbps per lane
- Aggregate throughput up to 10 Gbps in 4 data lanes
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MIPI D-PHY Tx 2 Lanes - TSMC7FF18, North/South Poly Orientation
- Compliant with the MIPI D-PHY specification, v1.2
- Fully integrated hard macro
- Up to 2.5 Gbps per lane
- Aggregate throughput up to 10 Gbps in 4 data lanes
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MIPI D-PHY Rx 4 Lanes - TSMC7FF18, North/South Poly Orientation
- Compliant with the MIPI D-PHY specification, v1.2
- Fully integrated hard macro
- Up to 2.5 Gbps per lane
- Aggregate throughput up to 10 Gbps in 4 data lanes
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MIPI D-PHY Rx 2 Lanes - TSMC7FF18, North/South Poly Orientation
- Compliant with the MIPI D-PHY specification, v1.2
- Fully integrated hard macro
- Up to 2.5 Gbps per lane
- Aggregate throughput up to 10 Gbps in 4 data lanes
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MIPI D-PHY Tx 2 Lanes - TSMC N7 1.8V, North/South Poly Orientation for Automotive, ASIL B Random, AEC-Q100 Grade 2
- Compliant with the MIPI D-PHY specification, v1.2
- Fully integrated hard macro
- Up to 2.5 Gbps per lane
- Aggregate throughput up to 10 Gbps in 4 data lanes
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MIPI D-PHY Rx 4 Lanes - TSMC 7FF18, North/South Poly Orientation for Automotive, ASIL B Random, AEC-Q100 Grade 2
- Compliant with the MIPI D-PHY specification, v1.2
- Fully integrated hard macro
- Up to 2.5 Gbps per lane
- Aggregate throughput up to 10 Gbps in 4 data lanes
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MIPI C-PHY v1.2 D-PHY v2.1 RX 3 trios/4 Lanes - TSMC7FF 1.8V, North/South Poly Orientation
- Compliant with the MIPI D-PHY specification, v2.1
- 4 Lanes in D-PHY mode up to 6.5Gb/s per lane
- Compliant with the MIPI C-PHY specification, v2.0
- 3 trios in C-PHY mode up to 6.5Gs/s per trio
