PLL IP for TSMC

Compare 819 PLL IP for TSMC from 27 vendors (1 - 10)

Ultra-Low Phase Noise Digital LC PLL
- Wideband integrated jitter <400fs in integer mode, <800fs in fractional mode with high-speed / clean reference with active fractional noise cancellation
Ultra-low Jitter Fractional-N Frequency Synthesizer PLL (5nm - 180nm)
- Jitter-Power optimized to meet PCIe1-5 reference clock requirements - replaces 300mW/$2.50 clock chip
- Low area on chip -- keepouts = DRC limit in most cases
Fractional-N Frequency Synthesizer PLL
- Wide functional range allows all frequencies in a system to be synthesized with one PLL macro
- Input & output frequency ranges greater than 1000:1
Analog-PLL For Spread Spectrum Clock
- TSMC 28nm HPM/HPC
- Including Loop-filter
- VCO operating range : 900MHz - 1800 MHz
Analog PLL For Frequency Multiplying
- Including Loop-filter
- VCO operating range : 2500MHz - 5000 MHz
- Output frequency range : 1250MHz - 2500 MHz
Analog-PLL For Frequency Multiplying
- Process: TSMC 28nm HPM/HPC
- Available metalization technologies: 4X2Y2R and 5X2Y2R
High Performance Fractional-N RF Frequency Synthesizer PLLs for 5G, WiFi, etc
- Fractional-N digital PLL architecture, using an LC-tank oscillator
Low Voltage, Low Power Fractional-N PLLs
- Low power, suitable for IoT applications
- Good jitter, suitable for clocking digital logic.
- Extremely small die area (< 0.005 sq mm), using a ring oscillator
- Output frequency can be from 1 to 400 times the input reference, up to 1.5GHz
General Purpose Fractional-N PLLs
- Low power, suitable for logic clocking applications
- Extremely small die area, using a ring oscillator
- Twelve bits fractional resolution
Fractional-N PLLs for Performance Computing
- Low jitter, suitable for many clocking applications, including high speed digital, ADC, DAC, medium-speed PHY
- Extremely small die area (< 0.005 sq mm), using a ring oscillator
- Output frequency can be from 1 to 400 times the input reference, up to 4GHz
- Reference clock from 10MHz to 500MHz