Clock Synthesizer IP for TSMC

Compare 5 Clock Synthesizer IP for TSMC from 3 vendors (1 - 5)

Filter:

Low Voltage, Low Power Fractional-N PLLs
- Low power, suitable for IoT applications
- Good jitter, suitable for clocking digital logic.
- Extremely small die area (< 0.005 sq mm), using a ring oscillator
- Output frequency can be from 1 to 400 times the input reference, up to 1.5GHz
General Purpose Fractional-N PLLs
- Low power, suitable for logic clocking applications
- Extremely small die area, using a ring oscillator
- Twelve bits fractional resolution
Fractional-N PLLs for Performance Computing
- Low jitter, suitable for many clocking applications, including high speed digital, ADC, DAC, medium-speed PHY
- Extremely small die area (< 0.005 sq mm), using a ring oscillator
- Output frequency can be from 1 to 400 times the input reference, up to 4GHz
- Reference clock from 10MHz to 500MHz
14GHz Integer-N High-Speed PLL
- Type II hybrid Integer-N LC-PLL
- Quadrature clocks at 14GHz and 7GHz
- Fast locking
Run Time Phase Alignment Circuit
- 1. Sync Clock Generation in one clock duation.
- 2. Generatted clock is Phase Aligned with the incoming data. Data can be received.
- 3. Tx and Rx Clock can be up to +/-5% off of the frequency range. This block can accomode and can generate same tx freq at the rx side.
- 4. This Rx Clock can be used to -