Die to Die IP for GLOBALFOUNDRIES
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Die to Die IP
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Die to Die IP
for GLOBALFOUNDRIES
from 4 vendors
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40G UltraLink D2D PHY
- Innovative mixed-signal architecture to achieve high bandwidth, ultra low latency and low power
- Flexible data rate from 20Gbps to 40Gbps
- Built-in self-test features to ensure “known good die”
- Interoperable between different technology nodes and foundries
- Easy routing and straightforward integration
- Achieves better than 10-15 bit error rate (BER) without requiring forward error correction (FEC)
- Integrated scrambling and lane de-skew functionality
- Supports -40ºC to 125ºC industrial temperature range
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Die-to-Die, 112G Ultra-Extra Short Reach PHY Ported to GF 12LP+ x8, North/South (vertical) poly orientation
- 16-lane TX and RX square macros for placement in any edge of the die
- Supports 2.5G to 112G data rates, enabling very high bandwidth per mm of beachfront for die-to-die and die-to-optical engine connectivity
- Implements NRZ and PAM-4 signaling
- Meets the performance, efficiency, and reliability requirements of die-to-die interconnects
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Die-to-Die, 112G Ultra-Extra Short Reach PHY in GF (12nm)
- Offers leading performance, power, and area / beachfront per terabit
- Includes 16 lanes of NRZ and PAM-4 transmitters or receivers
- Targeting the OIF XSR standards: CEI-112G and CEI-56G
- Implements robust clock forwarded and embedded clock recovery algorithms for additional flexibility
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Die-2-die interfaces for chiplets
- Analog I/Os
- ESD Power protection
- Ground pads
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INNOLINK-B PHY
- Support both Die2Die and Chip2Chip application
- GDDR6 like interface with IO voltage is core power supply (0.8V for TSMC 12nm)
- 24Gbps for maximum IO speed
- Default 16bit DQ Tx+ 16bit DQ Rx per module, module number can be 1/2/4/8/16 or more