The Enclustra Universal Drive Controller IP Core enables the easy addition of drive control capabilities to existing or future FPGA designs. There is no need for an extra drive controller chip that would consume precious PCB space and unnecessarily extend the project BOM.
Selecting Enclustra’s Universal Drive Controller IP Core for the drive control needs of future projects will significantly reduce time to market as well as the overall system cost.
Universal Drive Controller
Overview
Key Features
- Evaluation Kit available
- Support for DC, BLDC, 2- and 3-phase stepper motors
- Support for encoders and resolvers
- Field oriented control (FOC) for BLDC motors
- Completely autonomous error handling
- Optimized for lowest total solution cost
- Support for ADC-sharing between different devices
- Up to 8 drives per controller
- Up to 4 PID controllers per drive (position, velocity, current(s)) at up to 200kHz control rate
- Velocity- and acceleration-feed-forward
- Voltage, current and temperature supervision
- Separate PWM clock domain for high-resolution PWM
- Vendor-independent implementation
- Available with Avalon or AMBA-AXI interface
Benefits
- Significantly lower CPU load due to completely autonomous control loops
- Single-chip solution (fieldbus access, CPU and drive controller on the same chip)
- Easy integration, lowest solution cost
- Plenty of parallel processing power, zero jitter
- Well-defined interfaces for galvanically isolated power stages
- Great reusability due to configurable controller structure
Block Diagram
Applications
- Robotics
- Automation
- Medical diagnostics
- Semiconductor handling
- Automotive
Deliverables
- Universal Drive IP Core
- Netlist (please contact us for source code delivery conditions)
- Test bench (VHDL source code)
- User manual
- Universal Drive API
- C object and header files
- Application software example
- User manual