The SiFive U54-MC Standard Core is the world's first RISC-V application processor, capable of supporting full-featured operating systems such as Linux.
The U54-MC has 4x 64-bit U5 cores and 1x 64-bit S5 core - providing high performance with maximum efficiency. This core is an ideal choice for low-cost Linux applications such as IoT nodes and gateways, storage, and networking.
U54 MC Multicore: four U54 cores and one S51 core
Overview
Key Features
- Fully compliant with the RISC-V ISA specification
- 4x RV64GC U54 Application Cores
- 32KB L1 I-cache with ECC
- 32KB L1 D-cache with ECC
- 8 Region Physical Memory Protection
- 48 Local Interrupts per core
- Sv39 Virtual Memory support with 38 Physical Address bits
- 1x RV64IMAC S51 Monitor Core
- 16KB L1 I-Cache with ECC
- 8KB DTIM with ECC
- 8 Region Physical Memory Protection
- 48 Local Interrupts
- Fully Coherent TileLink Bus
- Integrated 2MB L2 Cache with ECC
- Real-time capabilities
- Both the L1 Instruction Cache and the L2 Cache can be configured into high speed deterministic SRAMs
- CLINT for multi-core timer and software interrupts
- PLIC with support for up to 511 interrupts with 7 priority levels
- Debug with instruction trace
- U54 Performance
- 2.87/1.7 DMIPS/MHz (Best Effort/Legal)
- 2.75 CoreMark/MHz
Block Diagram
Technical Specifications
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