TSMC CLN28HPC+ Derivative IP of IGASERT06A Enterprise Multi-Standard SerDes
Overview
The GUC's Quad-Lane EMS-XT PHY SerDes supports multiple high speed wire-line communication standards. Supported standards include CEI-28G-VSR, CEI-25G-LR, 100GBase-KR4 (IEEE 802.3bj), CPRI, and analogous backplane or chip-to-chip standards. In addition, EMS-XT PHY mantains backward compatibility supporting common legacy data rates at 10.3125G, 6.25G, 3.125G, 1.25G, and similar data rates. The receiver equalizes and recovers incoming serial data and de-serializes the data stream into selectable 10/16/20/32/40/64 bit-wide data bus. The transmitter, similarly, serializes selectable 10/16/20/32/40/64 bit-wide data bus and drives the serialized data off-chip with built-in adjustable de-emphasis (FFE). EMS SerDes includes the physical media attachment layer (PMA) which is implemented as a hard macro and the physical coding sub-layer (PCS) which may be licensed separately through GUC or its 3rd party partners.
Key Features
- PMAA
- RX Adaptive Decision Feedback Equalizer (DFE)
- Programmable Continuous Time Linear Equalizer (CTLE)
- RX Variable Gain Control
- RX Built-in fault detector (Loss-of-lock/Loss-of-signal)
- Adjustable TX de-emphasis (FFE)
- TX output amplitude control
- Supports RX Eye Monitor
- Supports JTAG 1149.6 boundary scan interface
- PMAD (PMA Digital) & Testability
- Built-in BIST functions (PRBS7,PRBS9,PRBS11,PRBS15,PRBS23,PRBS31 and User-Defined generators & checkers, etc.)
- Polarity inversion and bit reversal control
- Multiple Loopback modes
- Status registers
- Selectable TX/RX Data bit-wide control (10/20/40/16/32/64)
- LOL (loss of lock) detection
- LOS (loss of signal) detection
Technical Specifications
Foundry, Node
TSMC 28nm CLN28HPC+
Maturity
Avaiable on request
TSMC
Pre-Silicon:
28nm
HPCP
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