Single Port SRAM Compiler IP, UMC 55nm SP process
Overview
UMC 55nm SP/RVT+HVT Low-K Logic process synchronous high density Single Port SRAM memory compiler.
Technical Specifications
Foundry, Node
UMC 55nm SP
UMC
Pre-Silicon:
55nm
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- Single Port SRAM compiler - Memory optimized for high density and low power - Dual Voltage - compiler range up to 320 k
- Single Port SRAM compiler - Memory optimized for high density and low power - compiler range up to 640 k
- Single Port SRAM compiler - Memory optimized for high density and low power - compiler range up to 320 k