MIPI I3C Master IP

Overview

Key Features

• Compliant with MIPI I3C version 1.1 and I3C HCI version 1.1 specifications.
• Non HCI Version is also supported for designs which are gate count sensitive.
• Full MIPI I3C Master Functionality.
• Two wire serial interface up to 12.5 MHz using Push-Pull with the following Data rates supported:
• ->Standard speed
• Supports all topologies
• ->Single Master – Multi Slave
• ->Single Master – Single Slave
• ->Multi Master – Multi Slave
• ->Multi Master – Single Slave
• Dynamic Addressing while supporting Static Addressing for legacy I2C devices.
• Supports Master Pull up structures.
• Supports I3C address arbitration optimization.
• Supports Predictive addressing scheme
• Supports Direct commands
• Supports Direct command CCC framing
• Supports Single Data Rate (SDR) messaging.
• ->SDR with Direct CCC
• ->SDR with Broadcast CCC
• Supports High Data Rate (HDR) messaging
• ->HDR-Dual Data Rate Mode (HDR-DDR)
• ->HDR-Ternary symbol for Pure bus (HDR-TSP)
• ->HDR-Ternary symbol Legacy inclusive bus (HDR-TSL)
• In-Band Interrupt support and Hot-Join support
• Legacy I2C Device co-existence on the same Bus instance
• DMA interface support (DMA Mode)
• ->Single transfer descriptor defines Command and Data
• ->Single response status descriptor reports status of the transfer
• ->Linked descriptor support (Multicast messaging support)
• Auto-Reject for In-Band Interrupt and Hot-Join (NACK and directed DISEC CCC to disable)
• DMA Mode with Command Rings, to enable clean Doorbell mechanisms
• ->Multiple Command/Response Rings and IBI Rings, including IBI payload
• ->Supports for interrupt masking
• Fully synthesizable.
• Static synchronous design.
• Positive edge clocking and no internal tri-states.
• Scan test ready.
• Simple interface allows easy connection to microprocessor/microcontroller devices.

Benefits

• Single Site license option is provided to companies designing in a single site.
• Multi Sites license option is provided to companies designing in multiple sites.
• Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
• Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.

Deliverables

• The MIPI I3C Master interface is available in Source and netlist products.
• The Source product is delivered in verilog. If needed VHDL, SystemC code can also be provided.
• Easy to use Verilog Test Environment with Verilog Testcases
• Lint, CDC, Synthesis, Simulation Scripts with waiver files
• IP-XACT RDL generated address map
• Firmware code and Linux driver package
• Documentation contains User s Guide and Release notes.

Technical Specifications