MIPI D-PHY CSI-2 TX+ (Transmitter) IP in TSMC 28HPC+
Overview
The MXL-DPHY-CSI-2-TX+-T028HPC+-RF-ULL is a high-frequency low-power, source-synchronous, physical layer supporting the MIPI Alliance Specification for D-PHY v2.1, which is backward compatible with MIPI Specification for D-PHY v1.2. The PHY is configured as a MIPI master supporting Camera Serial interface CSI-2 v1.3. The High-Speed signals have a low voltage swing, while Low-Power signals have large swing. High-Speed functions are used for High-Speed data traffic while low power functions are mostly used for control.
Key Features
- Supports MIPI Specification for D-PHY Version 2.1
- Consists of 1 Clock lane and 4 Data lanes
- Supports both high speed and low-power modes
- 80 Mbps to 2.5 Gbps data rate in high speed mode
- 10 Mbps data rate in low-power mode
- Low power dissipation
- Testability support
Benefits
- The CSI-2 TX+ is a Mixel proprietary configuration that is optimized to support full-speed production and in-system testing while minimizing area and leakage power.
Block Diagram
Applications
- Mobile
- Cameras/Sensors
- IoT
- VR/AR/MR
- Consumer electronics
- Automotive
Deliverables
- Specifications
- GDSII
- LVS netlist
- LEF file
- IBIS Model
- Verilog Model
- Timing Model
- Integration Guidelines
- RTL
- Documentation
- One year support
Technical Specifications
Foundry, Node
TSMC 28nm HPC+
Maturity
Silicon Proven
Availability
Now
TSMC
Pre-Silicon:
28nm
HPCP
Related IPs
- MIPI D-PHY/LVDS Combo CSI-2 RX (Receiver) in TSMC 28HPC+
- MIPI D-PHY CSI-2 TX (Transmitter) in TSMC 28HPC+
- MIPI D-PHY IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
- MIPI D-PHY in ON Semiconductor 180nm
- MIPI D-PHY CSI-2 TX (Transmitter) in TSMC 28HPC+
- MIPI CSI-2 controller Receiver v 2.1, Compatible with MIPI C-PHY v1.2 & DPHY v2.1.