Low Power High Speed 1GHz Frac-N PLL IP Core

Overview

An ultra-low-power programmable fractional-N at 1GHz phase-locked loop (PLL) for frequency synthesis available at 28nm.

Key Features

  • Designed to be power-efficient
  • Fractional Division
  • High Resolution of 1GHz
  • Low Jitter
  • control the phase and frequency characteristics
  • Programmable Loop Filter
  • Lock Detection
  • Small Footprint

Deliverables

  • GDSII
  • LVS Spice netlist
  • Verilog model
  • LEF for clock generator
  • PLL
  • User Guidelines including: integration guidelines, layout guidelines, testability guidelines, packaging guidelines, board-level guidelines

Technical Specifications

Maturity
In Production
Availability
Immediate
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Semiconductor IP