Low Power High Speed 1.2GHz Frac-N PLL IP Core
Overview
A programmable on-the-fly Fractional-N PLL at 1.2GHz is required to lock to an incoming clock source and produce an output clock available at 40nm.
Key Features
- Designed to be power-efficient
- Fractional Division
- High Resolution of 1.2GHz
- Low Jitter
- control the phase and frequency characteristics
- Programmable Loop Filter
- Lock Detection
- Small Footprint
Deliverables
- GDSII
- LVS Spice netlist
- Verilog model
- LEF for clock generator
- PLL
- User Guidelines including: integration guidelines, layout guidelines, testability guidelines, packaging guidelines, board-level guidelines
Technical Specifications
Maturity
In Production
Availability
Immediate
Related IPs
- Low Power High Speed 1GHz Frac-N PLL IP Core
- Ultra low Power High Speed 800MHz Frac-N PLL IP Core
- Ultra low Power High Speed 600MHz lnteger-N PLL IP Core
- Ultra low Power High Speed 500MHz integer-N PLL IP Core
- Ultra low Power High Speed 400MHz lnteger-N PLL IP Core
- Ultra low Power High Speed 150MHz integer-N PLL IP Core