High Speed 1.5GHz Frac-N PLL IP Core
Overview
A programmable on-the-fly Fractional-N PLL at 1.5GHz is required to lock to an incoming clock source and produce an output clock available at 22nm
Key Features
- Up to 1.5Ghz clock output
- Wide range of multiplicand
- Small physical area
- TEST pin integrated
Deliverables
- GDSII
- LVS Spice netlist
- Verilog model
- LEF for clock generator
- PLL
- User Guidelines including: integration guidelines, layout guidelines, testability guidelines, packaging guidelines, board-level guidelines
Technical Specifications
Maturity
In Production
Availability
Immediate