The MI2Cv2 provides an interface between a microprocessor and an I2C bus that conforms to V2.1 of the I2C bus specification.
It can be programmed to operate as either a master or a slave device and performs arbitration in master mode to allow it to operate in multi-master systems.
In slave mode, it can interrupt the processor when it recognizes its own 7-bit or 10-bit address or the general call address.
The design supports both High speed (Hs) and Fast / Standard speed (F/S) transfer rates. The user may define the transfer rate using either two clock enable signals or a pair of clock control registers similar to that offered in the Inventra™ MI2C and MI2CV designs.
I2C V2 Bus Interface
Overview
Key Features
- Conforms to V2.1 of the I2C bus specification
- Supports High speed (3400kbits/s), Fast and Standard transfer rates
- Supports bus isolation
- Master or slave operation
- Multi-master systems supported
- Supports both 7-bit and 10-bit addressing on the I2C bus
- Performs arbitration and clock synchronization
- Own address and General Call address detection
- Interrupt on address detection
- Allows operation from a wide range of input clock frequencies
- 8-bit PVCI*-compatible synchronous CPU interface
- Fully synthesizable
- * Peripheral Virtual Component Interface, as defined by VSIA (OCB 2 v2.0)
Deliverables
- Verilog source code
- VHDL source code
- Synthesis script for Design Compiler
- Verilog & VHDL testbenches
- Reference technology netlist
- Product Specification & User Guide