I2C Bus Interface - Master with FIFO

Overview

Key Features

• Conforms to v.6.0 of the I2C specification
• Master operation Master transmitter
• Master receiver
• Support for all transmission speeds
• Standard (up to 100 kb/s)
• Fast (up to 400 kb/s)
• Fast Plus (up to 1 Mb/s)
• High Speed (up to 3,4 Mb/s)
• ULTRA-FAST (up to 5 Mb/s)
• Configurable FIFO size up to 256 Bytes
• Configurable SDA/SCL glitch filter
• Software programmable SDA/SCL bus timings
• Arbitration and clock synchronization
• Support for multi-master systems
• Support for both 7-bit and 10-bit addressing formats on the I2C bus
• Interrupt generation
• Allows operation from a wide range of input clock frequencies (build-in 12-bit clock timer)
• Available system interface wrappers:
• AMBA – APB Bus
• Altera Avalon Bus
• Xilinx OPB Bus
• Fully synthesizable
• Static synchronous design
• Positive edge clocking and no internal tri-states
• Scan test ready

Benefits

• Getting a sillicon proven IP
• Rapid prototyping and time-to-market reduction
• Design risk elimination
• Development costs reduction
• Full customization
• Technological independence (VHDL and Verilog)
• Global sales network
• Professional service

Applications

• Embedded microprocessor boards
• Consumer and professional audio/video
• Home and automotive radio
• Low-power applications
• Communication systems
• Cost-effective reliable automotive systems

Deliverables

• HDL Source Code
• Testbench environment
• Automatic Simulation macros
• Tests with reference responses
• Synthesis scripts
• Technical documentation
• 12 months of technical support

Technical Specifications