I2C Master/Slave Interface
Overview
CoreI2C provides an APB-driven serial interface, supporting I2C, SMBus, and PMBus data transfers. Several Verilog/VHDL parameters are available to minimize FPGA fabric area for a given application. CoreI2C also allows for multiple I2C channels, reusing logic across channels to reduce overall tile count.
Key Features
- Conforms to the Philips Inter-Integrated Circuit (I<sup>2</sup>C) v2.1 Specification (7-bit addressing format at 100 Kbps and 400 Kbps data rates)
- Supports SMBus v2.0 Specification
- Supports PMBus v1.1 Specification
- Data transfers up to at least 400 kbps nominally; faster rates can be achieved depending on external load and/or I/O pad circuitry
- Modes of operation configurable to minimize size
- Advanced Peripheral Bus (APB) register interface
- Multi-master collision detection and arbitration
- Own address and general call address detection
- Second Slave address decode capability
- Data transfer in multiples of bytes
- SMBus timeout and real-time idle condition counters
- IPMI 3 ms SCL low timeout
- Optional SMBus signals, SMBSUS_N and SMBALERT_N, controllable via APB IF
- Configurable spike suppression width
- Multiple channel configuration option
Technical Specifications
Related IPs
- I2C Bus Interface - Master/Slave
- I2C Master/Slave Controller Core IP
- Serial Peripheral Interface – Master/Slave with Octal, Quad, Dual and Single SPI Bus support
- I2C Bus Interface - Master with FIFO
- I2C V2 Bus Interface
- A bridge to convert the slave SPI interface to the master I2C interface and vice versa