HBM 3 Verification IP

Overview

Key Features

• Compliant to JEDEC HBM SDRAM Specification versionJESD235A.
• Supports Legacy and Pseudo Channel Mode.
• Supports connection to any HBM Memory Controller IPcommunicating with a JESD235A compliant HBM Memory Model.
• Available in all Stack memory size from 8 Gb to 32 Gb (8Channels/Stack).
• Available in Channel Density of 1 Gb(8 Banks/Channel), 2 Gb(8 Banks/Channel) or 4 Gb(16 Banks/Channel).
• Data-Bus width : 1024 (128 DQ width/per Channel).
• Supports Data Bus Inversion (DBIac) Feature.
• Supports Parity Checking for Command/Address bus & Databus.
• Supports Data Mask for masking Write data per byte.
• Supports configurable timing parameters and Channels-Dieassociations.
• Supports capturing all the valid HBM Row & Columncommands including Activate, Read, Write, Precharge insemi-independent way.
• Supports Power-up Reset and initialization sequences.
• Supports Power-Down, Self-Refresh operation.
• Reports various timing error signals, which can be used tocheck for any timing errors.
• Provides full control to the user to enable / disable varioustypes of messages.
• Integrates easily in any verification environment.
• Supports full timing models or bus functional models.
• Multiple instances of Monitor can be instantiated in aVerification Environment to support multiple Stacks.
• Supports advanced System Verilog features like constrainedrandom testing.
• Supports Callback / User Configuration in Monitor, Controllerand Memory Model BFMs.
• Supports wide variety of Error Injection scenarios.
• Supports Independent channel functioning.
• Supports Testport feature.

Benefits

• Available in native SystemVerilog(UVM/OVM/VMM) and Verilog.
• Unique development methodology toensure highest levels of quality.
• Availability of Compliance & Regression TestSuites.
• 24X5 customer support
• Unique and customizable licensing models
• Exhaustive set of assertions and coverpoints with connectivity example for all thecomponents.
• Consistency of interface, installation,operation and documentation across all ourVIPs.
• Provide complete solution and easyintegration in IP and SoC environment.

Block Diagram

Deliverables

• HBM Controller BFM
• HBM DRAM
• HBM Monitor and Scoreboard
• Test Environment & Test Suite:
  • Basic and Directed Protocol Tests
  • Random Tests
  • Error Scenario Tests
  • Assertions & Cover Point Tests
• Integration Guide, User Manual and Release Notes.

Technical Specifications