The Digital Blocks DB-eSPI-SPI-M-AMBA is a Serial Peripheral Interface (SPI) Controller Verilog IP Core supporting the addition of Enhanced SPI (eSPI) bus transfers to the standard SPI Master/Slave Controller. The DB-eSPI-SPI-M contains an AMBA AXI, AHB, or APB Bus Interface for interfacing a microprocessor to external eSPI or SPI Slave devices.
The DB-eSPI-SPI-M contains both eSPI and SPI Master functions. Programming the DB-eSPI-SPI-M lets it communicate with external eSPI or SPI Slaves. The eSPI Master Controller is a smaller VLSI footprint than the DB-eSPI-SPI-MS version, which supports both Master and Slave functions.
eSPI & SPI Master Controller w/FIFO
Overview
Key Features
- eSPI Features
- Master eSPI and standard Master SPI Modes (see below)
- eSPI Full Duplex Transfers - Command Phase followed by Response Phase
- Additional eSPI Signals to SPI Interface:
- RESET#
- ALERT#
- RESET# programmable as input or output
- ALERT# input interrupts CPU
- Support for interface up to 8 eSPI Slaves (Contact Digital Blocks if more needed)
- CRC-8 Generator on Transmit & Checker on Receive
- Compliance to eSPI Master function with Enhanced Serial Peripheral Interface (eSPI), Interface Base Specification, January 2016, Revision 1.0.
- SPI Features
- Master SPI Modes
- Full Duplex Transfers – Simultaneous Transmit & Receive
- Original 4 Signal Interface:
- MOSI - Master Output, Slave Input (Data)
- MISO - Master Input, Slave Output (Data)
- SCK - Serial Clock
- SS[N:0] - Slave Select
- Configurable SPI Modes for 1/2/4/ Data Lanes: (Optional):
- Standard SPI Mode (1 Data Lane)
- Dual SPI Mode (2 Data lanes)
- Quad SPI Mode (4 Data Lanes)
- 3-wire SPI Interface (Optional)
- Up to N=8 Slave Select (SS) Outputs for multiple Slaves on SPI Bus
- Programmable SPI Frame Formats:
- Programmable Words-Per-Frame (1 to Full Depth of FIFO)
- Programmable LSB-first or MSB-first frames
- Configurable FIFO depth for off-loading the SPI transfers from the processor:
- Separate Transmit / Receive FIFOs
- Two Clock Domains:
- AMBA Bus / SCK Clocks
- Clock Generator - Master Mode:
- Two Clock Sources
- Programmable Baud Rate
- Programmable Clock Phase & Polarity
- Master / S Independent Clock Domains
- Internal interrupts with masking control
- Optional DMA Controller for transfers between User Memory & SPI Bus
- Enhanced Error Detection & Protection
- Available AMBA Microprocessor Interfaces:
- AXI / AHB / APB Buses
- 8 / 16 / 32 bit Data Interface
- Compliance with ARM AMBA and Freescale / Motorola SPI specifications:
- Fully-synchronous, synthesizable Verilog RTL core, with rising-edge clocking, no gated clocks, and no internal tri-states, for easy integration into FPGA or ASIC design flows.
Deliverables
- Verilog or VHDL RTL Source or technology-specific netlist.
- Comprehensive testbench suite with expected results.
- Synthesis scripts.
- Installation & Implementation Guide.
- Technical Reference Manual.
Technical Specifications
Maturity
Successful in Customer Implementations
Availability
Immediately
Related IPs
- SPI Master / Slave Controller w/FIFO (APB Bus)
- SPI Master / Slave Controller w/FIFO (AHB & AHB-Lite Bus)
- SPI Master / Slave Controller w/FIFO (AXI & AXI-Lite Bus)
- SPI Master Controller w/FIFO (AHB & AHB-Lite Bus)
- SPI Master Controller w/FIFO (APB Bus)
- eSPI & SPI Master/Slave Controller w/FIFO (APB, AHB, or AXI Bus)