eSPI & SPI Master/Slave Controller w/FIFO (APB, AHB, or AXI Bus)

Overview

Key Features

• ** eSPI Features **
• Master & Slave eSPI and standard Master/Slave SPI Modes (see below)
• eSPI Full Duplex Transfers - Command Phase followed by Response Phase
• eSPI Slave supports eSPI Bus Protocol and Transaction and Link Layer requirements
• Additional eSPI Signals to SPI Interface:
• RESET#
• ALERT#
• RESET# programmable as input or output
• ALERT# input interrupts CPU
• Support for interface up to 8 eSPI Slaves (Contact Digital Blocks if more needed)
• CRC-8 Generator on Transmit & Checker on Receive
• Compliance to eSPI Master function with Enhanced Serial Peripheral Interface (eSPI), Interface Base Specification, January 2016, Revision 1.0.
• ** SPI Features **
• Master and Slave SPI Modes
• Full Duplex Transfers – Simultaneous Transmit & Receive
• Original 4 Signal Interface:
• MOSI - Master Output, Slave Input (Data)
• MISO - Master Input, Slave Output (Data)
• SCK - Serial Clock
• SS[N:0] - Slave Select
• Configurable SPI Modes for 1/2/4/ Data Lanes: (Optional):
• Standard SPI Mode (1 Data Lane)
• Dual SPI Mode (2 Data lanes)
• Quad SPI Mode (4 Data Lanes)
• 3-wire SPI Interface (Optional)
• Up to N=8 Slave Select (SS) Outputs for multiple Slaves on SPI Bus
• Programmable SPI Frame Formats:
• Programmable Words-Per-Frame (1 to Full Depth of FIFO)
• Programmable LSB-first or MSB-first frames
• Configurable FIFO depth for off-loading the SPI transfers from the processor:
• Separate Transmit / Receive FIFOs
• Two Clock Domains:
• AMBA Bus / SCK Clocks
• Clock Generator - Master Mode:
• Two Clock Sources
• Programmable Baud Rate
• Programmable Clock Phase & Polarity
• Master / Slave Independent Clock Domains
• Internal interrupts with masking control
• Optional DMA Controller for transfers between User Memory & SPI Bus
• Enhanced Error Detection & Protection
• Available AMBA Microprocessor Interfaces:
• AXI / AHB / APB Buses
• 8 / 16 / 32 bit Data Interface
• Compliance with ARM AMBA and Freescale / Motorola SPI specifications:
• Fully-synchronous, synthesizable Verilog RTL core, with rising-edge clocking, no gated clocks, and no internal tri-states, for easy integration into FPGA or ASIC design flows.

Deliverables

• Verilog or VHDL RTL Source or technology-specific netlist.
• Comprehensive testbench suite with expected results.
• Synthesis scripts.
• Installation & Implementation Guide.
• Technical Reference Manual.

Technical Specifications