Digital Cell Library TSMC

Overview

The agileDSCL is a compact digital standard cell library customizable for specific foundries and processes, and optimized for low-power, ultra-low-leakage, high-density or high-speed applications.

It provides a selection of standard cells with functionalities essential to implement digital designs, with additional power management library to support the implementation of low-power designs.

Please contact Agile Analog to discuss specialized libraries

Agile Analog designs are based on tried and tested architectures to ensure reliability and functionality. Our design methodology is programmatic, systematic and repeatable leading to analog IP that is more verifiable, more robust and more reliable.
Our methodology also allows us to quickly re-target our IP to different process options. We support all the major foundries including TSMC, GlobalFoundries, Samsung Foundry and SMIC as well as other IC foundries and manufacturers. Please contact Agile Analog for further information.

Key Features

Compact standard cell library targeting a wide range of foundries and processes
Customized for low-power, ultra-low-leakage, high density or high-speed applications with choices of:

Multiple VT and channel length
Thick-Oxide based cells
Various track heights

Power Management library for low-power designs
Timing models for customizable range of PVT
High Quality library with class leading validation and models compatible with industry standard tools

Benefits

Optimized for PPA targets / DFM

DFM-optimized

Customization

Agile Analog’s COMPOSA tool enables efficient creation of libraries for specific foundries, processes, and cell architectures.
Possibility to generate models at customized PVT corners

Block Diagram

Applications

IoT, Security, Automotive, AI, SoCs, ASICs

Deliverables

Datasheet
Testing and Integration Guide
Verilog Models
Floorplan (LEF)
Timing models (LIB)
Netlist (CDL)
Layout (GDS)
Physical Verification Report
Design Report

Technical Specifications

Foundry, Node

TSMC

Pre-Silicon: 3nm , 4nm , 5nm , 6nm , 7nm , 10nm , 12nm , 16nm , 20nm , 22nm , 28nm , 28nm HP , 28nm HPC , 28nm HPCP , 28nm HPL , 28nm HPM , 28nm LP , 40nm G , 40nm LP , 45nm GS , 45nm LP , 55nm FL , 55nm G , 55nm GP , 55nm LP , 55nm NF , 55nm ULP , 55nm ULPEF , 55nm UP , 65nm G , 65nm GP , 65nm LP , 80nm , 80nm GT , 80nm HS , 85nm , 90nm FS , 90nm FT , 90nm G , 90nm GOD , 90nm GT , 90nm LP , 90nm zzz , 110nm G , 110nm HV , 110nm LVP , 130nm , 130nm BCD , 130nm BCD+ , 130nm G , 130nm LP , 130nm LV , 130nm LVOD , 150nm G , 150nm LV , 160nm G , 160nm LP , 180nm , 180nm E , 180nm ELL , 180nm FG , 180nm G , 180nm LP , 180nm LV , 180nm ULL

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