Automotive MIPI A-PHY Source IP - 1-Lane

Overview

Key Features

• Compliant with MIPI A-PHY specification version 1.0
• Support Gear-2 up to 4Gbps
• Support data bus width: 20-bit parallel interface
• Support 1 lane
• Support Uplink Receiver @ 100Mbps
• Selectable input clock frequency: 25MHz
• Maximum output clock frequency at 200MHz
• Supports Single-ended coaxial or shielded twisted-pair (STP) cable up to 15m
• Support A-PHY PMD layer by HARD macro
• Support AEC-Q100 (Grade 1) for automotive applications
• High performance Data and clock recovery.
• Analog monitor port for test and debug
• Embedded termination Resistor and optional calibration function
• Supporting Link IP CD12911IP200 (PHY layer PCS, RTS and Data Link) soft macro Native Protocol Adaption layer supports (Option)

Benefits

• CL12911 and CL12912 support MIPI A-PHY interface.
• A-PHY is long-reach, serializer-deserializer (SerDes) physical layer interface for automotive applications such as advanced driver assistance systems, autonomous driving systems and other surround-sensor applications, including cameras and in-vehicle infotainment displays. A-PHY forms a family of specifications designed to provide end-to-end connectivity with safety and security built-in.
• With a reach of up to 15 meters, MIPI A-PHY offers high-speed performance with an ultra-low packet error rate for unprecedented reliability, ultra-high immunity to electromagnetic interference effects.

Applications

• Automotive Application
• Advanced driver assistance systems
• Autonomous driving systems
• Surround-sensor applications
• Camera
• Display

Deliverables

• GDSII
• Place-Route views (.LEF)
• Liberty library (.lib)
• Verilog behavior model
• Netlist & Timing information
• Datasheet, Packaging and Layout Guideline / PCB Guideline
• LVS/DRC verification reports
• Static Delay Analysis (STA) Guideline
• Testing Guideline (Option)Testing Guideline (Option)

Technical Specifications