APB bus to Fusion analog interface
Overview
CoreAI (Analog Interface) allows for easy control of the on-chip analog hardware peripherals within the Fusion family of Microsemi devices. Control may be implemented with an internal or external microprocessor or microcontroller (such as Core8051 or CoreMP7), or with user-created custom logic within the FPGA fabric. The industry-standard AMBA (Advanced Microcontroller Bus Architecture) APB (Advanced Peripheral Bus) slave interface is used as the primary control mechanism within CoreAI. Like all DirectCores, CoreAI is designed, verified and fully supported to make it easy to use enabling designers to get their products to market faster.
Key Features
- ADC Conversions Controlled by MCU/MPU Writes
- AMBA APB Slave Interface (8- or 16-Bit Data Widths Supported)
- 14 Maskable Interrupt Sources
- Internal Clock Divider for Generating Analog Configuration MUX Clock
- Optional Read FIFO Stores up to 256 ADC Conversion Results
- Analog Configuration MUX Can Be Configured by SmartGen
- User Can Easily Modify User Testbench Using Existing Format to Add Custom Tests