AHB to APB Mailbox Interface
Overview
CoreMBX (Mail Box) allows data messages (mail) to pass back and forth from one processing element to another. The user is able to choose whether this message passing capability is implemented with one or more instances of dual-port SRAM hard macros, or with one or more instances of FIFO hard macros. The first processing element, such as Cortex-M1, connected to the first bus uses CoreMBX to initialize and pass messages back and forth to a second processing element, such as CoreABC or Core8051s, that uses a set of AMBA 2 or AMBA 3 advanced peripheral bus (APB) slave connections. Note that the first bus may be asynchronous to the second bus; therefore synchronization logic is included internally. CoreMBX Block Diagram
Key Features
- Simultaneously accessible from an AMBA AHB/AHB-Lite master and an AMBA 2 APB master
- Mailbox memory storage elements made of either dual-port SRAM or FIFO blocks
- Init/Config master interface suitable for initializing CoreABC via AHB/AHB-Lite master
- Configurable number of interrupt flags between two processors
- Optional ROM built of FPGA tiles for up to 40 16-bit ROM words
Block Diagram
