Memory Controller & PHY IP
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Memory Controller & PHY IP
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285
Memory Controller & PHY IP
from 51 vendors
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10)
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ONFI 5.0 PHY
- The PHY design supports the newly introduced NV-LPDDR4 mode along with SDR, NV_DDR, and NV_DDR2, NV_DDR3 mode.
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xSPI NOR Flash controller
- Memory mapped access to the connected flash devices
- Continuous Burst transfer support
- Auto boot support
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ONFI Flash Controller
- AXI System Interface
- NAND Flash
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ONFI 4.1 NAND Flash Controller & PHY & IO Pads on 16nm
- Page Size – 2KB, 4KB, 8KB, 16KB
- Bank/chip select options
- Programmable timing
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ONFI 4.1 NAND Flash Controller & PHY & IO Pads on 28nm
- Page Size – 2KB, 4KB, 8KB, 16KB
- Bank/chip select options
- Programmable timing
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ONFI 4.1 NAND Flash Controller & PHY & IO Pads on 12nm
- Page Size – 2KB, 4KB, 8KB, 16KB
- Bank/chip select options
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Hyperbus Flash Memory Controller
- Compatible with spansion hyperbus based memory products.
- 0 Wait State Write Burst Operation for HyperBus memory on AXI interface of up to 256 words.
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ONFI 4.0 NAND Flash Controller & PHY
- • Support ONFI 4.0, EZ – NAND, Standard ClearNAND, Advanced ClearNAND
- • Support standard asynchronous NAND flash
- • High performance from 40MT/s to 800MT/s
- • High density NAND flash up to 1024 Gb
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Universal NandFlash Controller
- ONFI 5.X Compliant
- SLC / MLC / TLC
- SDR modes 0 to 5
- NVDDR modes 0 to 5
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eMMC 5.1 Host Controller
- Compliant with eMMC Specification Version 5.0
- Supports one of the following System/Host Interfaces: AHB, AXI or OCP
