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SDRAM Controller IP

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Compare 127 SDRAM Controller IP from 14 vendors (1 - 10)
  • DDR3 SDRAM Memory Controller
    • Supports DDR3 SDRAM memory devices on AMD-Xilinx 7 Series FPGAs
    • Size optimized – ideal for low cost 7 Series FPGAs (Artix-7, Spartan-7)
    Block Diagram -- DDR3 SDRAM Memory Controller
  • DO-254 SDRAM Controller
    • Design Assurance Level A according to RTCA DO-254/ED-80 (April, 2000)
    • Compliant to JEDEC Standard No. 21-C Page 3.11.5.1 Release 12
    • Single clock domain fully synchronous design
    • Configurable to support any SDRAM device
    Block Diagram -- DO-254 SDRAM Controller
  • LPDDR3 SDRAM Controller
    • Interfaces to Industry Standard LPDDR3 SDRAM components and modules compliant with the JESD-209.3 specification
    • High-Performance LPDDR3 performance, up to 400 MHz/800 Mbps operation
    • Supports automatic LPDDR3 SDRAM initialization and refresh
    • Supports Deep Power Down Mode
    Block Diagram -- LPDDR3 SDRAM Controller
  • LPDDR SDRAM Controller
    • Interfaces to industry standard LPDDR SDRAM according to JESD209B
    • Double-data rate architecture; two data transfers per clock cycle
    • Bi-directional data strobe per byte of data (DQS)
    • Programmable auto refresh support
    Block Diagram -- LPDDR SDRAM Controller
  • DDR3 SDRAM Controller
    • Support for all LatticeECP3 “EA” devices
    • Interfaces to Industry Standard DDR3 SDRAM components and modules compliant with JESD79-3, DDR3 SDRAM Standard
    • Interfaces to DDR3 SDRAM at speeds up to 400 MHz / 800 Mbps in -8 speed grade devices
    • Supports memory data path widths of -8, -16, -24, -32, -40, -48, -56, -64 and -72 bits
    Block Diagram -- DDR3 SDRAM Controller
  • DDR/DDR2 SDRAM Controller MACO Core
    • ispLEVER version 7.1 or later
    • MACO design kit
    • MACO license file
    Block Diagram -- DDR/DDR2 SDRAM Controller MACO Core
  • DDR SDRAM Controller - Pipelined for ispXPGA and ORCA4
    • Performance of Greater than 100MHz (200 DDR)
    • Interfaces to JEDEC Standard DDR SDRAMs
    • Supports DDR SDRAM Data Widths of 16, 32 and 64 Bits
    • Supports up to 8 External Memory Banks
    Block Diagram -- DDR SDRAM Controller - Pipelined for ispXPGA and ORCA4
  • DDR SDRAM Controller - Non-Pipelined
    • Performance of Greater than 133MHz (266 DDR)
    • Interfaces to JEDEC Standard DDR SDRAMs
    • Supports DDR SDRAM Data Widths of 16, 32 and 64 bits
    • Supports up to 8 External Memory Banks
    Block Diagram -- DDR SDRAM Controller - Non-Pipelined
  • AHB Internal SRAM Controller
    • AMBA® AHB Compatible
    • Handles byte, half, and word (8,16,32bit) accesses to internal SSRAM
    • Can be used with Internal Flash or OTP Memory
    • Zero wait state / low latency operation
    Block Diagram -- AHB Internal SRAM Controller
  • SDRAM/SRAM/FLASH Memory Controller
    • Memory Interface
    • Wishbone Interface
    • Core Internals
    Block Diagram -- SDRAM/SRAM/FLASH Memory Controller
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