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AHB-Lite General Purpose Memory Module
- Full support for AMBA 3 AHB-Lite protocol
- Fully parameterized
- User-defined address and byte-aligned data widths supported
- Configurable memory depth, limited only by target technology capability
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Cache controller including Retention Ready feature for fast CPU wake-up time and very low power consumption
- TSMC Soft IP qualification (IP9000)
- Straightforward connection
- Support of AHB-Lite interfaces to ensure fast and smooth integration in any MCU subsystem without need for any bridge
- External TAG and Cache memories to improve portability across a wide range of process technologies
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Frame Rate Converter for 4K
- TMC’s FRUC utilizes “MEMC” algorithm optimized by DMNA.
- Extremely small generations of halo, judder, and artifact on the interpolating frames.
- 2:2 pull down and 2:3 pull down detections are implemented.
- Processing functions for motionless section, scrolling ticker, and screen edge are implemented.
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Universal Multiport Memory Controller - LPDDR 3/2 Controller
- Compliant with AXI V4.0 specification
- Compliant with DFI 3.1 specification
- Compliant with JEDEC LPDDR2 and LPDDR3 standards
- Support for 8, 16, 32 SDRAM bus width, for a total memory data path width up to 64 bits
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Cache controller including Retention Ready feature for fast CPU wake-up time and very low power consumption
- TSMC Soft IP qualification (IP9000)
- First cache controller optimized for low power
- Performance optimization (optional)
- Apparent frequency is accelerated up to 11 times
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Direct Memory Access Controller
- 32-bit or 8-bit internal registers access
- 32-bit transmission address range
- Transaction size from 1B up to 16MB
- Four transmission channels
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Cache controller for fast NVM memories access and very low power consumption
- TSMC Soft IP qualification (IP9000)
- Straightforward connection
- Support of AMBA 3 AHB-Lite interfaces to ensure fast and smooth integration in any MCU subsystem without need for any bridge
- External TAG and Cache memories to improve portability across a wide range of process technologies
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QDR IV XP PHY + Memory Controller
- Standard: QDR IV XP (Extreme Performance) PHY and Memory Controller
- Frequency: Memory Interface : 800MHz
- User Interface : 200MHz
- Write Latency at Memory Interface : 5 Full Rate Cycles
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Slave side SPI/QPI controller 133MHZ
- SPI
- QPI (Quad I/O SPI)
- 133MHz
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SD Card Host Controller
- Meets SD Host Controller Standard Specification Version 2.00
- Supports single and multiple SD cards
- Compliant to CoreConnect(TM) PLB bus
- Parametrizable VHDL design