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DDR5 Controller IP

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Compare 39 DDR5 Controller IP from 11 vendors (1 - 10)
  • GDDR6 Controller
    • Supports up to 24 Gb/s per pin operation
    • Can handle two x16 GDDR6 channels with one controller or independently with two controllers
    • Supports x8 or x16 clamshell mode
    • Queue-based interface optimizes performance and throughput
    • Maximizes memory bandwidth and minimizes latency via Look-Ahead command processing
    • Automatic retry on transactions where EDC error detected
    Block Diagram -- GDDR6 Controller
  • High Performance DDR5/4/3 Memory Controller
    • Compliant with AXI4 Specification
    • Compliant with DFI 3.1 Specification
    • Compliant with JEDEC DDR3, DDR3L, DDR4 and DDR5 standards
    • Supports 64, 32, 16 and 8 bit Memory SDRAM for DDR3L, DDR4 and DDR5
    Block Diagram -- High Performance DDR5/4/3 Memory Controller
  • GDDR6 Memory Controller IP
    • JEDEC GDDR6 standard JESD250B
    • Fast frequency switching
    • Flexible Configuration
    Block Diagram -- GDDR6 Memory Controller IP
  • DDR Controller
    • Sideband and in-line SEC/DED ECC
    • Supports advanced RAS features including error scrubbing, parity, etc.
    • Compliant to LPDDR5/4X/4/3 and DDR5/4/3 protocol memories
    • Memory controller interface complies with DFI standards up to version 5.0
    • Priority per command on Arm® AMBA® 4 AXI, AMBA 3 AXI
    • Single and multi-port host interface options
    • QoS features allow command prioritization on Arm AMBA 4 AXI and CHI interfaces
    • Silicon proven and shipping in volume
    Block Diagram -- DDR Controller
  • DDR/LPDDR Controller
    • Sideband and in-line SEC/DED ECC
    • Supports advanced RAS features including error scrubbing, parity, etc.
    • Compliant to LPDDR5/4X/4/3 and DDR5/4/3 protocol memories
    • Memory controller interface complies with DFI standards up to version 5.0
    • Priority per command on Arm® AMBA® 4 AXI, AMBA 3 AXI
    Block Diagram -- DDR/LPDDR Controller
  • GDDR5 Synthesizable Transactor
    • Supports 100% of GDDR5 protocol standard JESD212C
    • Supports all the GDDR5 commands as per the specs
    • Supports all types of timing and protocol violation detection
    • Supports up to 8GB device density
    Block Diagram -- GDDR5 Synthesizable Transactor
  • DDR5 DFI Synthesizable Transactor
    • Compliant with DFI 5.0 Specification.
    • DFI-DDR5 Applies to :
    • DDR5 protocol standard JESD79-5 & JESD79-5 Rev1.40 (Draft) Specifications
    • Supports all Interface Groups.
    Block Diagram -- DDR5 DFI Synthesizable Transactor
  • DDR5 Synthesizable Transactor
    • Supports 100% of DDR5 protocol standard JESD79-5 & JESD79-5 Rev1.40 (Draft)
    • Supports all the DDR5 commands as per the specs
    • Supports up to 64GB device density
    • Supports the following devices:
    Block Diagram -- DDR5 Synthesizable Transactor
  • DDR5 DFI Verification IP
    • Compliant with DFI 5.0 Specification.
    • DFI-DDR5 Applies to :
    • DDR5 protocol standard JESD79-5 & JESD79-5 Rev1.40 (Draft) Specifications
    • Supports all Interface Groups.
    Block Diagram -- DDR5 DFI Verification IP
  • DDR5 NVRAM Memory Model
    • Supports DDR5 NVRAM memory devices from all leading vendors.
    • Supports 100% of DDR5 NVRAM protocol standard JESD79-5 (Draft).
    • Supports all the DDR5 NVRAM commands as per the specs.
    • Supports up to 1 TB device density.
    Block Diagram -- DDR5 NVRAM Memory Model
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