MIPI SPMI IP
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14
MIPI SPMI IP
from 5 vendors
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10)
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MIPI SPMI Controller or Target
- The SPMI-CTRL core implements a highly featured, easy-to-use controller for the MIPI System Power Management Interface (MIPI-SPMI) bus.
- It supports the latest version (v2.0) of the MIPI-SPMI specification, and is suitable for the implementation of either controller or target nodes in an SPMI bus.
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Simulation VIP for MIPI SPMI
- Topology
- Multiple subordinates and multiple mains topology
- Clock
- High Speed and Low Speed device classes
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MIPI SPMI Verification IP
- Supports 1.0 and 2.0 MIPI SPMI Specification.
- Full MIPI SPMI Master and Slave functionality.
- Operates as a Master, Slave, or both.
- Monitor, Detects and notifies the testbench of all protocol and timing errors.
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MIPI SPMI Synthesizable Transactor
- Supports 1.0 and 2.0 MIPI SPMI Specification
- Supports Full MIPI SPMI Master and Slave functionality
- Operates as a Master, Slave, or both
- Supports all topologies as per the MIPI SPMI specification
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MIPI SPMI PSVIP
- Supports 1.0 and 2.0 MIPI SPMI Specification.
- Supports Full MIPI SPMI Master and Slave functionality.
- Operates as a Master, Slave, or both.
- Supports all topologies as per the MIPI SPMI specification.
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MIPI SPMI Slave DMA IIP
- Supports 2.0 and 1.0 MIPI SPMI Specification
- Full MIPI SPMI Slave functionality
- Supports following frames
- Command Frame
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MIPI SPMI Slave AXI Bridge IIP
- Supports 2.0 and 1.0 MIPI SPMI Specification
- Full MIPI SPMI Slave functionality
- Allows external devices to access the internal AXI Bus
- Supports following frames
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MIPI SPMI Slave AHB Bridge IIP
- Supports 2.0 and 1.0 MIPI SPMI Specification
- Full MIPI SPMI Slave functionality
- Supports following frames
- Command Frame
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MIPI SPMI Slave IIP
- Supports 2.0 and 1.0 MIPI SPMI Specification
- Full MIPI SPMI Slave functionality
- Supports following frames
- Command Frame
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MIPI SPMI Master IIP
- Supports 2.0 and 1.0 MIPI SPMI Specification
- Full MIPI SPMI Master functionality
- Supports following frames
- Command Frame