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Fibre Channel 8G, 4G, 2G IP

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Compare 11 Fibre Channel 8G, 4G, 2G IP from 4 vendors (1 - 10)
  • Fibre Channel ULP (Upper Layer Protocol) Core
    • FC-AE-RDMA & FC-AV compliant interface with hardware-based offload
    • Hardware DMA engines map sequence data to host memory buffers
    Block Diagram -- Fibre Channel ULP (Upper Layer Protocol) Core
  • Fibre Channel ASM (Anonymous Subscriber Messaging) Core
    • Message label validation checks performed in hardware
    • Multiple user modes for receiving messages, including strictly mapped message-to-buffer and free-buffer implementations
    • Transmit message chaining options provided
    • Complete set of registers for managing core and configuring core options
    Block Diagram -- Fibre Channel ASM (Anonymous Subscriber Messaging) Core
  • Fibre Channel Link Layer Core
    • Complete FC1-FC2 functionality
    • Intuitive streaming user interface
    • Scales for multiple port designs
    Block Diagram -- Fibre Channel Link Layer Core
  • UDP/IP Hardware Protocol Stack - 1G
    • 1 GbE network links, including 100/100 MbE (triple play)
    • Low latency, high-performance wire-line performance
    • Internet Protocol (IP) Packet Processor:
    • User Datagram Protocol (UDP) Packet Processor:
  • UDP/IP Hardware Protocol Stack - 10G
    • 10 GbE network links
    • Low latency, high-performance wire-line performance
    • Internet Protocol (IP) Packet Processor:
    • User Datagram Protocol (UDP) Packet Processor:
  • UDP/IP Hardware Protocol Stack - 25G
    • 25 GbE network links
    • Low latency, high-performance wire-line performance
    • Internet Protocol (IP) Packet Processor:
    • User Datagram Protocol (UDP) Packet Processor:
  • UDP/IP Hardware Protocol Stack - 40G
    • 40 GbE network links
    • Low latency, high-performance wire-line performance
    • Internet Protocol (IP) Packet Processor:
    • User Datagram Protocol (UDP) Packet Processor:
  • UDP/IP Hardware Protocol Stack - 50G
    • 50 GbE network links
    • Low latency, high-performance wire-line performance
    • Internet Protocol (IP) Packet Processor:
    • User Datagram Protocol (UDP) Packet Processor:
  • Synthesized RTL of FiberChannel controller IP-core
    • ANSI INCITS 424-2007 support with 1.0625/2.125/4.25 GBaud data rates
    • Built-in scatter-gather DMA engine for FC frames receiver/transmitter queues
    • Built-in CRC calculation on transmitted frames and checks on received frames
    • FC frame length check with up to 16K max frame length support
  • Run Time Phase Alignment Circuit
    • 1. Sync Clock Generation in one clock duation.
    • 2. Generatted clock is Phase Aligned with the incoming data. Data can be received.
    • 3. Tx and Rx Clock can be up to +/-5% off of the frequency range. This block can accomode and can generate same tx freq at the rx side.
    • 4. This Rx Clock can be used to -
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Semiconductor IP