Multi-Protocol PHY IP for UMC
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Multi-Protocol PHY IP
for UMC
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MIPI C-PHY/D-PHY Combo Universal IP in UMC 40LP
- Dual mode PHY can support C-PHY and D-PHY
- Supports MIPI Specification for D-PHY Version 1.2
- Supports MIPI Specification for C-PHY Version 1.0
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12G Ethernet PHY in UMC (28nm)
- Physical Coding Sublayer (PCS) block with PIPE interface
- Supports PCIe 6.0 (PAM-4), 5.0, 4.0, 3.1, 2.1, 1.1 encoding, backchannel initialization
- Supports x1, x2, x4, x8, and x16 hard macro configurations
- Lane margining at the receiver