MIPI D-PHY IP for UMC
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MIPI D-PHY IP
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MIPI D-PHY IP
for UMC
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MIPI C-PHY/D-PHY Combo Universal IP in UMC 40LP
- Dual mode PHY can support C-PHY and D-PHY
- Supports MIPI Specification for D-PHY Version 1.2
- Supports MIPI Specification for C-PHY Version 1.0
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MIPI D-PHY Universal IP in UMC 40LP
- Consists of 1 Clock lane and up to 4 Data lanes
- Supports the MIPI Standard 1.1 for D-PHY
- Supports both high speed and low-power modes
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MIPI D-PHY Rx IP, Silicon Proven in UMC 55LP
- Compliant to MIPI Alliance Standard for D-PHY specification Version 1.2
- Supports standard PPI interface compliant to MIPI Specification
- Supports synchronous transfer at high-speed mode with a bit rate of 80-2500 Mb/s
- Supports asynchronous transfer at low power mode with a bit rate of 10 Mb/s
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MIPI D-PHY Tx IP, Silicon Proven in UMC 55LP
- Compliant to MIPI Alliance Standard for
- D-PHY specification Version 1.2
- Supports standard PPI interface compliant to MIPI Specification
- Supports synchronous transfer at high-speed mode with a bit rate of 80-2500 Mb/s
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MIPI D-PHY Tx-Only 4 Lanes in UMC (28nm, 22nm)
- Compliant with the MIPI D-PHY specification
- Fully verified hard macro
- Up to 2.5 Gb/s per lane
- Aggregate throughput up to 10 Gb/s in 4 data lanes
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MIPI D-PHY Rx-Only 4 Lanes in UMC (28nm, 22nm)
- Compliant with the MIPI D-PHY specification
- Fully verified hard macro
- Up to 2.5 Gb/s per lane
- Aggregate throughput up to 10 Gb/s in 4 data lanes
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MIPI D-PHY Rx-Only 2 Lanes in UMC (28nm)
- Compliant with the MIPI D-PHY specification
- Fully verified hard macro
- Up to 2.5 Gb/s per lane
- Aggregate throughput up to 10 Gb/s in 4 data lanes
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MIPI DPHY DSI TX IP
- Compliant with MIPI® Alliance Specification for Display Serial Interface (DSI) V1.2
- Compliant with MIPI® Alliance Standard for Display Bus Interface (DBI) V2.0
- Compliant with MIPI® Alliance Standard for Display Pixel Interface (DPI) V2.0
- Compliant with MIPI® Alliance Specification for D-PHY V1.2
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MIPI D-PHY TX Combo TTL PHY
- Analog mixed-signal hard-macro HS/LP transmitter solution
- Compliant with MIPI® Alliance Specification for D-PHY V1.2
- Integrated PHY Protocol Interface (PPI) supports interfaces to CSI, DSI and UniPro™ MIPI® protocols
- HS, LP, ULPS, and TTL modes supported
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MIPI D-PHY TX
- Analog mixed-signal hard-macro HS/LP transmitter solution
- Compliant with MIPI® Alliance Specification for D-PHY V1.2
- Integrated PHY Protocol Interface (PPI) supports interfaces to CSI, DSI and UniPro™ MIPI® protocols
- HS, LP, ULPS modes supported