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MIPI D-PHY IP for UMC

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Compare 31 MIPI D-PHY IP for UMC from 7 vendors (1 - 10)
  • MIPI C-PHY/D-PHY Combo Universal IP in UMC 40LP
    • Dual mode PHY can support C-PHY and D-PHY
    • Supports MIPI Specification for D-PHY Version 1.2
    • Supports MIPI Specification for C-PHY Version 1.0
    Block Diagram -- MIPI C-PHY/D-PHY Combo Universal IP in UMC 40LP
  • MIPI D-PHY Universal IP in UMC 40LP
    • Consists of 1 Clock lane and up to 4 Data lanes
    • Supports the MIPI Standard 1.1 for D-PHY
    • Supports both high speed and low-power modes
    Block Diagram -- MIPI D-PHY Universal IP in UMC 40LP
  • MIPI DPHY_RX v1.2, 2C4D, UMC 28HPC+, E/W orientation
    • Compliant with MIPI D-PHY specification up to v1.2/v1.1 (by different process nodes)
    • Supports MIPI DSI and CSI-2 protocols
    • Supports HS data rates up to 2.5Gbps (v1.2, per lane) . 1.5Gbps(v1.1, per lane)
    • Supports LS data rate of 10Mbps and Ultra-low power modes
    Block Diagram -- MIPI DPHY_RX v1.2, 2C4D, UMC 28HPC+, E/W orientation
  • MIPI DPHY_TX v1.2, 1C4D, UMC 28HPC+, E/W orientation
    • Compliant with MIPI D-PHY specification up to v1.2/v1.1 (by different process nodes)
    • Supports MIPI DSI and CSI-2 protocols
    • Supports HS data rates up to 2.5Gbps (v1.2, per lane) . 1.5Gbps(v1.1, per lane)
    • Supports LS data rate of 10Mbps and Ultra-low power modes
    Block Diagram -- MIPI DPHY_TX v1.2, 1C4D, UMC 28HPC+, E/W orientation
  • MIPI D-PHY Rx IP, Silicon Proven in UMC 55LP
    • Compliant to MIPI Alliance Standard for D-PHY specification Version 1.2
    • Supports standard PPI interface compliant to MIPI Specification
    • Supports synchronous transfer at high-speed mode with a bit rate of 80-2500 Mb/s
    • Supports asynchronous transfer at low power mode with a bit rate of 10 Mb/s
    Block Diagram -- MIPI D-PHY Rx IP, Silicon Proven in UMC 55LP
  • MIPI D-PHY Tx IP, Silicon Proven in UMC 55LP
    • Compliant to MIPI Alliance Standard for
    • D-PHY specification Version 1.2
    • Supports standard PPI interface compliant to MIPI Specification
    • Supports synchronous transfer at high-speed mode with a bit rate of 80-2500 Mb/s
    Block Diagram -- MIPI D-PHY Tx IP, Silicon Proven in UMC 55LP
  • MIPI D-PHY Tx-Only 4 Lanes in UMC (28nm, 22nm)
    • Compliant with the MIPI D-PHY specification
    • Fully verified hard macro
    • Up to 2.5 Gb/s per lane
    • Aggregate throughput up to 10 Gb/s in 4 data lanes
  • MIPI D-PHY Rx-Only 4 Lanes in UMC (28nm, 22nm)
    • Compliant with the MIPI D-PHY specification
    • Fully verified hard macro
    • Up to 2.5 Gb/s per lane
    • Aggregate throughput up to 10 Gb/s in 4 data lanes
  • MIPI D-PHY Rx-Only 2 Lanes in UMC (28nm)
    • Compliant with the MIPI D-PHY specification
    • Fully verified hard macro
    • Up to 2.5 Gb/s per lane
    • Aggregate throughput up to 10 Gb/s in 4 data lanes
  • MIPI DPHY DSI TX IP
    • Compliant with MIPI® Alliance Specification for Display Serial Interface (DSI) V1.2
    • Compliant with MIPI® Alliance Standard for Display Bus Interface (DBI) V2.0
    • Compliant with MIPI® Alliance Standard for Display Pixel Interface (DPI) V2.0
    • Compliant with MIPI® Alliance Specification for D-PHY V1.2
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