MIPI PHY IP for UMC
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MIPI PHY IP
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48
MIPI PHY IP
for UMC
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MIPI C-PHY/D-PHY Combo Universal IP in UMC 40LP
- Dual mode PHY can support C-PHY and D-PHY
- Supports MIPI Specification for D-PHY Version 1.2
- Supports MIPI Specification for C-PHY Version 1.0
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MIPI D-PHY Universal IP in UMC 40LP
- Consists of 1 Clock lane and up to 4 Data lanes
- Supports the MIPI Standard 1.1 for D-PHY
- Supports both high speed and low-power modes
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MIPI M-PHY v4.1 IP, Silicon Proven in UMC 28 HPC
- Compliant with M-PHY Spec 4.1, UniPro Spec 1.8, UFS Spec 3.0
- Support HS-MODE Gear4(A/B) with data rate up to 11.6Gb/s, and backward compatible
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MIPI M-PHY v3.1 IP, Silicon Proven in UMC 40LP
- Compliant with M-PHY Spec 4.1, UniPro Spec 1.8, UFS Spec 3.0
- Support HS-MODE Gear4(A/B) with data rate up to 11.6Gb/s, and backward compatible
- Support LS-MODE PWM-G1 to PWM-G5 with data rate up to 144Mb/s
- Support reference clock frequency with 19.2/26/38.4/52MHz defined in UFS spec.
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MIPI D-PHY Rx IP, Silicon Proven in UMC 55LP
- Compliant to MIPI Alliance Standard for D-PHY specification Version 1.2
- Supports standard PPI interface compliant to MIPI Specification
- Supports synchronous transfer at high-speed mode with a bit rate of 80-2500 Mb/s
- Supports asynchronous transfer at low power mode with a bit rate of 10 Mb/s
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MIPI D-PHY Tx IP, Silicon Proven in UMC 55LP
- Compliant to MIPI Alliance Standard for
- D-PHY specification Version 1.2
- Supports standard PPI interface compliant to MIPI Specification
- Supports synchronous transfer at high-speed mode with a bit rate of 80-2500 Mb/s
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MIPI M-PHY Compliant (HS-G2) IP
- Complies with MIPI Standard for M-PHY, Draft Specification v0.90.
- Dual-simplex point-to-point interface with ultra low voltage differential signaling
- Slew-rate control for EMI reduction
- Supports all HS modes (GEAR 1-2)
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MIPI D-PHY Tx-Only 4 Lanes in UMC (28nm, 22nm)
- Compliant with the MIPI D-PHY specification
- Fully verified hard macro
- Up to 2.5 Gb/s per lane
- Aggregate throughput up to 10 Gb/s in 4 data lanes
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MIPI D-PHY Rx-Only 4 Lanes in UMC (28nm, 22nm)
- Compliant with the MIPI D-PHY specification
- Fully verified hard macro
- Up to 2.5 Gb/s per lane
- Aggregate throughput up to 10 Gb/s in 4 data lanes
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MIPI D-PHY Rx-Only 2 Lanes in UMC (28nm)
- Compliant with the MIPI D-PHY specification
- Fully verified hard macro
- Up to 2.5 Gb/s per lane
- Aggregate throughput up to 10 Gb/s in 4 data lanes