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DDR5 IP for TSMC

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Compare 329 DDR5 IP for TSMC from 10 vendors (1 - 10)
  • GDDR6 PHY IP for 12nm
    • JEDEC JESD250 compliant GDDR6 support
    • X16 mode, X8 mode, and pseudo-channel mode
    • Low frequency RDQS mode support
    Block Diagram -- GDDR6 PHY IP for 12nm
  • DDR5/4 PHY for TSMC 7nm
    • Application optimized configurations for fast time to delivery and lower risk
    • Memory controller interface complies with DFI standards up to 5.0
    • Internal and external datapath loop-back modes
    • Per-bit deskew on read and write datapath
    Block Diagram -- DDR5/4 PHY for TSMC 7nm
  • DDR/LPDDR PHY
    • DDR5/4/3 training with write-leveling and data-eye training
    • Optional clock gating available for low-power control
    • Internal and external datapath loop-back modes
    • I/O pads with impedance calibration logic and data retention capability
    • Programmable per-bit (PVT compensated) deskew on read and write datapaths
    • RX and TX equalization for heavily loaded systems
    Block Diagram -- DDR/LPDDR PHY
  • DDR5/4 PHY V2 - TSMC N7
    • Supports JEDEC standard DDR5 and DDR4 SDRAMs
    • High-performance DDR PHY supporting data rates up to 8400 Mbps
    • PHY independent, firmware-based training using an embedded calibration processor
    • Supports up to 4 trained states/ frequencies with <3μs switching time
    Block Diagram -- DDR5/4 PHY V2 - TSMC N7
  • DDR5/4 PHY V2 - TSMC N6
    • Supports JEDEC standard DDR5 and DDR4 SDRAMs
    • High-performance DDR PHY supporting data rates up to 8400 Mbps
    • PHY independent, firmware-based training using an embedded calibration processor
    • Supports up to 4 trained states/ frequencies with <3μs switching time
    Block Diagram -- DDR5/4 PHY V2 - TSMC N6
  • DDR5/4 PHY V2 - TSMC N5
    • Supports JEDEC standard DDR5 and DDR4 SDRAMs
    • High-performance DDR PHY supporting data rates up to 8400 Mbps
    • PHY independent, firmware-based training using an embedded calibration processor
    • Supports up to 4 trained states/ frequencies with <3μs switching time
    Block Diagram -- DDR5/4 PHY V2 - TSMC N5
  • DDR5 PHY - TSMC N5
    • Supports JEDEC standard DDR5 and DDR4 SDRAMs
    • High-performance DDR PHY supporting data rates up to 8400 Mbps
    • PHY independent, firmware-based training using an embedded calibration processor
    • Supports up to 4 trained states/ frequencies with <3μs switching time
    Block Diagram -- DDR5 PHY - TSMC N5
  • DDR5 PHY - TSMC N4P
    • Supports JEDEC standard DDR5 and DDR4 SDRAMs
    • High-performance DDR PHY supporting data rates up to 8400 Mbps
    • PHY independent, firmware-based training using an embedded calibration processor
    • Supports up to 4 trained states/ frequencies with <3μs switching time
    Block Diagram -- DDR5 PHY - TSMC N4P
  • DDR5 PHY - TSMC N3P
    • Supports JEDEC standard DDR5 and DDR4 SDRAMs
    • High-performance DDR PHY supporting data rates up to 8400 Mbps
    • PHY independent, firmware-based training using an embedded calibration processor
    • Supports up to 4 trained states/ frequencies with <3μs switching time
    Block Diagram -- DDR5 PHY - TSMC N3P
  • DDR5 MRDIMM2 PHY - TSMC N3P
    • Supports JEDEC standard DDR5 and DDR4 SDRAMs
    • High-performance DDR PHY supporting data rates up to 8400 Mbps
    • PHY independent, firmware-based training using an embedded calibration processor
    • Supports up to 4 trained states/ frequencies with <3μs switching time
    Block Diagram -- DDR5 MRDIMM2 PHY - TSMC N3P
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