DDR2 IP for TSMC
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LPDDR PHY
- Application-optimized configurations for fast time to delivery and lower risk
- Low-power VDD idle, VDD light sleep, and power-efficient clocking in low-speed modes
- I/O pads with impedance calibration logic and data-retention capability
- Fine-grain custom delay cell for delay tuning
- Internal and external datapath loop-back modes
- RX and TX equalization for heavily loaded systems
- Programmable per-bit (PVT compensated) deskew on read and write datapaths