XAUI PHY

Overview

The Innosilicon XAUI PHY is a highly programmable module that processes high-speed serial data to parallel data compatible with the IEEE802.3 standard. The PHY supports XAUI physical layer specifications.
The PHY module includes a top level wrapper integrating both the Physical Media Attachment (PMA) layer, and the Physical Coding Sub-Block (PCS) layer.

Key Features

Idle is substituted as K,R or A in Transmit Direction
K,R and A are substituted back to Idle in Receive Direction
Sequenced Ordered Sets might be received and stored, then are transmitted when Idle on the bus
Bit Lock and COMMA Synchronization
De-skew between Lanes
Programmable Parameter Registers
Auto Calibration on Termination Resistors
Reduced XAUI support

Benefits

As with all Innosilicon IP, the focus is on silicon proven, fully certified solutions providing:
Small size
Low power
High ATE coverage
Simple integration
Flexible customization

Applications

10G Ethernet Physical
RXAUI Physical
Single Lane Available @3.125Gbps

Technical Specifications

Foundry, Node

Samsung 14/10/8nm, GF 55/22/14/12nm, SMIC 55/40/14nm, TSMC 55/40/22/16/12nm, UMC 55/40/28/22nm, HLMC 40nm

Maturity

Silicon proven and in volume production

Availability

now

GLOBALFOUNDRIES

In Production: 12nm , 14nm LPP , 22nm FDX , 55nm LPX
Silicon Proven: 12nm , 14nm LPP , 22nm FDX , 55nm LPX

SMIC

In Production: 14nm , 40nm LL , 55nm LL
Silicon Proven: 14nm , 40nm LL , 55nm LL

Samsung

In Production: 8nm , 10nm , 14nm
Silicon Proven: 8nm , 10nm , 14nm

TSMC

In Production: 12nm , 16nm , 22nm , 40nm G , 40nm LP , 55nm LP
Silicon Proven: 12nm , 16nm , 22nm , 40nm G , 40nm LP , 55nm LP

UMC

In Production: 22nm , 28nm HPC
Silicon Proven: 22nm , 28nm HPC

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