This document introduces the low power Innosilicon Video-by-One (VBO) Receiver IP containing PHY and controller. Innosilicon VBO RX is designed for receiving video data from the host device. Innosilicon VBO RX supports maximum 16 data lanes with each lane up to 4Gbps, which can carry signals at pixel clock frequency from 20MHz to 300MHz.
Innosilicon VBO RX contains analog circuits with programmable termination, equalization and clock data recovery circuit to receive data from a standard VBO source device. Innosilicon VBO RX contains all VBO components including I/Os and the data symbol de-serialization unit.
Video-by-One Receiver IP_16ch
Overview
Key Features
- Compliant with V-by-One HS Standard Version 1.4
- Supports 1/2/4/8/16-lane configuration
- Supports 3/4/5-byte mode
- Supports data rate up to 4Gbps per lane
- Supports pixel clock frequency from 20MHz to 300MHz
- Hot Plug Detect and Sink Lock Detect
- APB Configuration Interface
- Embedded IO pads with ESD
- Programmable termination, equalization and clock data recovery circuit
Benefits
- Low power consumption
- Fully customizable
- Small area
- Simple integration process
- Available options include:
- Test chips and test boards
- FPGA integration support
- Chip level integration support
Technical Specifications
Foundry, Node
SMIC 40nm
SMIC
In Production:
40nm
LL
Silicon Proven: 40nm LL
Silicon Proven: 40nm LL
TSMC
In Production:
40nm
LP
Silicon Proven: 40nm LP
Silicon Proven: 40nm LP
UMC
In Production:
40nm
Silicon Proven: 40nm
Silicon Proven: 40nm
Related IPs
- MIPI CSI-2 Receiver
- MIPI D-PHY CSI-2 RX (Receiver) IP
- GLONASS/GPS/Galileo/BeiDou multisystem single-band 2-channel receiver RFIC
- Dual FPD-link, 30-Bits Color LVDS Receiver, 170Mhz (SVGA/FHD@120Hz) LVDS de-serializer 10:70 channel decompression with automatic de-skew
- MIPI D-PHY DSI RX (Receiver) IP
- ASI Receiver