Power clamp ESD solutions
Rail clamp ESD protection
0.75V domain
Small area
Small area rail clamp for FinFET
Overview
Key Features
- ESD protection cells
Benefits
- Scalable robustness
- Area efficient - 66% smaller compared to traditional approach
Applications
- Every IC design that requires a special ESD protection
Deliverables
- GDSII
- LVS support
- Datasheet
- Documentation
- Integration guidelines and services
Technical Specifications
Foundry, Node
All foundries and processes
Maturity
Silicon proven
Availability
Immediate
TSMC
Pre-Silicon:
4nm
,
5nm
,
6nm
,
7nm
,
10nm
,
12nm
,
16nm
,
22nm
,
28nm
,
28nm
HP
,
28nm
HPC
,
28nm
HPCP
,
28nm
HPL
,
28nm
HPM
,
28nm
LP
,
40nm
G
,
40nm
LP
,
45nm
GS
,
45nm
LP
,
55nm
FL
,
55nm
G
,
55nm
GP
,
55nm
LP
,
55nm
NF
,
55nm
ULP
,
55nm
ULPEF
,
55nm
UP
,
65nm
G
,
65nm
GP
,
65nm
LP
Silicon Proven: 3nm
Silicon Proven: 3nm
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