MIPI D-PHY Universal IP in TSMC 28HPC+
Overview
The MXL-DPHY-UNIV-T-28HPC+ is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification for D-PHYv2.5. The PHY can be configured as a MIPI Master or MIPI Slave supporting camera interface CSI-2 and display interface DSI/DSI-2. The PHY supports mobile, IoT, virtual reality, and automotive applications
Key Features
- Supports MIPI Alliance Specification for D-PHY Version 2.5
- Consists of 1 Clock lane and 4 Data lanes
- Embedded, high performance, and highly programmable PLL
- Supports both low-power mode and high speed mode with integrated SERDES
- 80 Mbps to 1.5 Gbps data rate per lane without skew calibration in D-PHY mode
- 2.5 Gbps data rate per lane with skew calibration in high speed D-PHY mode
- 10 Mbps data rate in low-power mode
- Low power dissipation
- Testability support including internal loopback
- Calibrator for resistance termination
Benefits
- The Mixel MIPI D-PHY Universal IP is a superset that contains all the subblocks for D-PHY CSI-2 TX, D-PHY CSI-2 RX, D-PHY DSI-2 TX, and D-PHY DSI-2 RX.
Block Diagram
Applications
- Mobile
- Displays
- Cameras/Sensors
- IoT
- VR/AR/MR
- Consumer electronics
- Automotive
Deliverables
- Specifications
- GDSII
- LVS netlist
- LEF file
- IBIS Model
- Verilog Model
- Timing Model
- Integration Guidelines
- RTL
- Documentation
- One year support
Technical Specifications
Foundry, Node
TSMC 28HPC+
Maturity
Upon Request
Availability
Now
Related IPs
- MIPI D-PHY IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
- MIPI D-PHY / C-PHY Combo IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
- MIPI D-PHY/LVDS Combo CSI-2 RX (Receiver) in TSMC 28HPC+
- DDR4/ LPDDR4/ DDR3L PHY IP - 1866Mbps (Silicon Proven in TSMC 28HPC+)
- MIPI D-PHY Rx-Only 2 Lanes in TSMC (40nm, 28nm, 22nm, 16nm, 12nm, N7, N6)
- MIPI D-PHY Rx-Only 4 Lanes in TSMC (40nm, 28nm, 22nm, 16nm, 12nm, N7, N6)