MIPI D-PHY DSI RX (Receiver) in UMC 22ULP/22ULL
Overview
The MXL-DPHY-DSI-RX-U-22ULP-22ULL is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification for D-PHY v2.5. The PHY can be configured as a MIPI Slave supporting display interface DSI/DSI-2. The PHY supports mobile, IoT, virtual reality, and automotive applications.
Key Features
- Supports MIPI Alliance Specification for D-PHY Version 2.5
- Consists of 1 Clock lane and 4 Data lanes
- Supports both low-power mode and high-speed mode with integrated SERDES
- 80 Mbps to 1.5 Gbps data rate per lane without skew calibration in D-PHY mode
- 2.5 Gbps data rate per lane with skew calibration in high-speed D-PHY mode
- 10 Mbps data rate in low-power mode
- Low power dissipation
- Testability support
Benefits
- Area and performance optimized for DSI RX.
Block Diagram
Applications
- Mobile
- Displays
- IoT
- VR/AR/MR
- Consumer electronics
- Automotive
Deliverables
- Specifications
- GDSII
- LVS netlist
- LEF file
- IBIS Model
- Verilog Model
- Timing Model
- Integration Guidelines
- RTL
- Documentation
- One year support
Technical Specifications
Foundry, Node
UMC, 22ULP-22ULL
Maturity
Available Upon Request
Availability
Available Upon Request
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