MIPI C-PHY RX PHY

Overview

The Innosilicon MIPI C-PHY provides a C-PHY in a single IP core, which integrates a compatible PHY that supports high speed data receiver, plus a MIPI® low-power low speed transceiver that supports data transfer in the bi-directional mode. The C-PHY was designed to coexist on the same IC pins as D-PHY so that dual-mode devices could be developed with low power signaling like D-PHY. This allows a seamless implementation allowing interface to C-PHY based sensors. The Innosilicon I/O and ESD are also built-in as one in a rectangular footprint for any configuration. It is optimized for high-speed applications with robust timing and small silicon area.
The C-PHY supports the electrical portion of MIPI C-PHY 1.1 standard, covering all transmission modes (ULP/LP/HS). The Innosilicon MIPI CPHY cost-effectively adds MIPI C-PHY 1.1 capability to any SoC used in communication and consumer electronics field.

Key Features

  • Analog mixed-signal hard-macro LP/HS Receiver solution
  • Compliant with MIPI Alliance Standard for C-PHY specification v1.1.
  • Integrated PHY Protocol Interface (PPI) supports interfaces to CSI, DSI and UniPro™ MIPI® protocols
  • Expandable to support 3 data trios
  • HS, LP, and ULP modes supported
  • 2.5Gsps maximum data transfer rate per trio on C-PHY mode
  • 10Mbps per lane in low-power mode
  • Unidirectional mode supported
  • ECC and CRC insertion supported
  • Automatic termination control for HS and LP modes
  • Low-Power dissipation: less than 2mA per trio/lane in HS RX mode
  • Buffers with tunable On-Die-Termination

Deliverables

  • Databook and physical implementation guides Netlist (Spice format for LVS)
  • Library Exchange Format (LEF)
  • Verilog Models
  • GDSII to Foundry IP Merge
  • Module integration guidelines
  • Silicon validation report (when available)
  • Evaluation board (when available)

Technical Specifications

Foundry, Node
SMIC 28nm
SMIC
In Production: 28nm
Silicon Proven: 28nm
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Semiconductor IP