HSIC PHY
Overview
The Innosilicon HSIC PHY is fully compliant with the High-Speed Inter-Chip Supplement to the USB 2.0 Specification. By stripping off all the legacy USB overhead, this PHY is the size of a few IO pads and passes data at 480Mb/s, while leveraging the existing USB 2.0 software stack. Optimized for both area and power, it contains all the necessary PHY components such as IO's and ESD.
Key Features
- Consumes <90mW during data transfer
- Consumes <50uW when not transferring data
- Uses standard chip digital and IO supplies
- Low pin count
- Designed to fit into a GPIO ring
- Compliant with the High-Speed Inter-Chip Supplement to the USB 2.0 Specification
- Data rate of 480 Mb/s
- Standard UTMI+ interface to controller
- Integrated Low jitter, fixed bandwidth PLL
- Includes BIST, loop back and boundary scan
- Easily ported into any technology
Benefits
- Low power consumption
- Fully customizable
- Small area
- Simple integration process
- Available options include
- Test chips and test boards
- FPGA integration support
- Chip level integration
Applications
- Application processor interfaces
- PCB Embedded devices
Deliverables
- We can provide the following deliverables to aid quick and reliable integration into the design flow. Please contact us for any additional views:
- GDSII
- Netlist (Spice format for LVS)
- Footprint (LEF format)
- User documentation
- Module integration guidelines
- Datasheet
- Silicon validation report
- Evaluation board
Technical Specifications
Foundry, Node
GF 55/28/22/14/12nm, SMIC 55/40/28/14nm, Samsung 14nm, TSMC 55/40/28/22nm, UMC 55/40/28/22nm, HLMC 40/28nm
Maturity
Silicon proven and in production
Availability
now
GLOBALFOUNDRIES
In Production:
12nm
,
14nm
LPP
,
22nm
FDX
,
28nm
SLP
,
55nm
LPX
Silicon Proven: 12nm , 14nm LPP , 22nm FDX , 28nm SLP , 55nm LPX
Silicon Proven: 12nm , 14nm LPP , 22nm FDX , 28nm SLP , 55nm LPX
SMIC
In Production:
14nm
,
28nm
HKC+
,
40nm
LL
,
55nm
LL
Silicon Proven: 14nm , 28nm HKC+ , 40nm LL , 55nm LL
Silicon Proven: 14nm , 28nm HKC+ , 40nm LL , 55nm LL
Samsung
In Production:
14nm
Silicon Proven: 14nm
Silicon Proven: 14nm
TSMC
In Production:
22nm
,
28nm
HPC
,
28nm
HPCP
,
28nm
HPM
,
40nm
G
,
40nm
LP
,
55nm
LP
Silicon Proven: 22nm , 28nm HPC , 28nm HPCP , 28nm HPM , 40nm G , 40nm LP , 55nm LP
Silicon Proven: 22nm , 28nm HPC , 28nm HPCP , 28nm HPM , 40nm G , 40nm LP , 55nm LP
UMC
In Production:
22nm
,
28nm
HPC
,
40nm
LP
,
55nm
Silicon Proven: 22nm , 28nm HPC , 40nm LP , 55nm
Silicon Proven: 22nm , 28nm HPC , 40nm LP , 55nm
Related IPs
- USB HSIC PHY - High Speed Inter-Chip IP Core
- UCIe-S PHY for Standard Package (x16) in TSMC N3E, North/South Orientation
- LPDDR5X/5/4X PHY - TSMC N5A for Automotive, ASIL B Random, AEC-Q100 Grade 2
- Die-to-Die, 112G Ultra-Extra Short Reach PHY Ported to TSMC N5 X8, North/South (vertical) poly orientation
- UCIe-S PHY for Standard Package (x16) in SS SF5A, North/South Orientation
- HBM3 PHY V2 - TSMC N5