DP1.2 Transmitter PHY

Overview

Innosilicon DP TX IP is designed to transmit video, audio and auxiliary data from system host device to a display device for display applications.
Innosilicon DP TX IP contains the digital logic and the physical layer. The digital logic receives video and auxiliary data from the controller and outputs these data to physical layer for further process.
The physical layer contains the main link, the AUX channel, PLL, and bias circuit. The main link contains 4 high speed data channels to transmit video and other stream data. Each data channel consists of serializer and driver. The serializer converts the parallel input data to 1-bit high speed serial stream and the driver converts the digital serial data to low swing differential signals with typical AC-coupled connection. The data rate is up to 5.4Gbps per channel.
The AUX channel employs half-duplex, bidirectional link to transmit and receive auxiliary information, such as EDID information and link status, between a transmitter and a receiver device. PLL generates the clocks required by data channels and the digital logic. The bias circuit generates voltage and current reference.
Innosilicon DP TX IP offers reliable implementation for DisplayPort interface, which can be integrated in the SOC used in multimedia device.

Key Features

  • Area: 0.68mm2 including IO and ESD
  • Note: The area parameter is for reference only. Please refer to the final LEF file for the actual values.
  • Compliant with DP1.2 and eDP1.4 specifications
  • Typical 27MHz reference clock
  • Support 1/2/4-lane configuration
  • Up to 5.4Gbps data rate per data channel
  • Support 20-bit parallel input up to 270MHz for each data lane
  • Support AUX channel working in 1MHz Manchester-II coding mode
  • Support programmable output swing, termination and pre-emphasis
  • Support BIST logic
  • APB slave interface for internal register access
  • Built-in low jitter PLL and bandgap reference

Benefits

  • Low power consumption
  • Fully customizable
  • Small area
  • Simple integration process
  • Available options include:
    • Test chips and test boards
    • FPGA integration support
    • Chip level integration

Deliverables

  • Datasheet
  • Physical Integration Guide
  • Timing Library Model (LIB)
  • Encrypted Verilog Model
  • Library Exchange Format (LEF)
  • GDSII Database
  • Evaluation Board if Available

Technical Specifications

Foundry, Node
SMIC 40/28nm
SMIC
In Production: 28nm , 40nm LL
×
Semiconductor IP